fix(intel): solve s10 warm reset issue

This is extension of the patch to fix the warm
reset issue in agilex refer to this commit 7f4fa931a.

The warm reset not able to trigger due to the system
not

fix(intel): solve s10 warm reset issue

This is extension of the patch to fix the warm
reset issue in agilex refer to this commit 7f4fa931a.

The warm reset not able to trigger due to the system
not able to detect the magic number. ATF only able
to solve for boot core. For secondary cores, Linux
need to update psci driver to WFI the cores in EL3.
Original Linux WFI is EL1.
Thus causing secondary cores not working.

Change-Id: Iee5e3f6d3334832fe432721fcf7b872534334988
Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>

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refactor(arm): unify SPSR retrieval logic

Consolidate platform-specific SPSR setup logic into a single
arm_get_spsr() function that accepts an image_id to select between BL32
and BL33. This reduces

refactor(arm): unify SPSR retrieval logic

Consolidate platform-specific SPSR setup logic into a single
arm_get_spsr() function that accepts an image_id to select between BL32
and BL33. This reduces duplication and simplifies control over SPSR
generation for later stages, particularly BL33.

The SPD remains responsible for setting the SPSR for BL32.

Change-Id: Ibbba708d607e7676989f5c7ceffe33d7bb2195f1
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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feat(fvp): enable kernel dt convention

Enable USE_KERNEL_DT_CONVENTION for the FVP platform to pass the DT blob
(DTB) in x0 to BL33. This aligns with the Linux boot protocol as
described in Document

feat(fvp): enable kernel dt convention

Enable USE_KERNEL_DT_CONVENTION for the FVP platform to pass the DT blob
(DTB) in x0 to BL33. This aligns with the Linux boot protocol as
described in Documentation/arm64/booting.rst.

In addition:

- Clean up legacy ARM_LINUX_KERNEL_AS_BL33 handling since
USE_KERNEL_DT_CONVENTION now implies this mode for DT handoff.
- Override args.arg0 for BL33 to point to ARM_PRELOADED_DTB_BASE in
RESET_TO_BL31.
- Skip setting the primary MPID in x0 when using this convention.

Change-Id: Ieea8cfe68104b82038b9311613abf13afe7b48f1
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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Merge changes from topics "refactor_stmm", "stmm_crb_area", "stmm_with_xferlist" into integration

* changes:
feat(fvp): organize fvp_stmm_manifest.dts
feat(juno): add pseudo CRB area
feat(fvp)

Merge changes from topics "refactor_stmm", "stmm_crb_area", "stmm_with_xferlist" into integration

* changes:
feat(fvp): organize fvp_stmm_manifest.dts
feat(juno): add pseudo CRB area
feat(fvp): add pseudo CRB area
feat(arm): add pseudo CRB area
feat(juno): increase xtable for pseudo CRB
feat(fvp): increase xtable for pseudo CRB for SPMC_AT_EL3
feat(el3-spmc): deliver TPM event log via hob list
feat(el3-spmc): get sp_manifest via xferlist
feat(fvp): tos_fw_config with transfer list
feat(arm): load tos_fw_cfg using xferlist in SPMC_AT_EL3
feat(fvp): increase secure partition's table mapping count
feat(fvp): increase bl2 mmap tables for handoff

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Merge changes Ib220a866,I38e6af65,I1554efdb,Iae99985e,I96f96267, ... into integration

* changes:
feat(stm32mp25-fdts): enable rng nodes for ST boards
feat(stm32mp2): prepare DDR secure area encr

Merge changes Ib220a866,I38e6af65,I1554efdb,Iae99985e,I96f96267, ... into integration

* changes:
feat(stm32mp25-fdts): enable rng nodes for ST boards
feat(stm32mp2): prepare DDR secure area encryption
feat(stm32mp2): add some platform helpers
feat(st-drivers): add RISAF driver
feat(fdts): add RISAF nodes for STM32MP25
feat(stm32mp2-fdts): add memory firewall node
feat(stm32mp2-fdts): add firewall nodes in fw-config
feat(stm32mp2): add RIF dt-binding defines
feat(stm32mp1-fdts): add MCE support for STM32MP13 DK board
feat(stm32mp1): prepare DDR secure area encryption for STM32MP13
feat(stm32mp1): enable MCE driver for STM32MP13
feat(st-drivers): add Memory Cipher Engine driver
feat(dt-bindings): add MCE DT bindings for STM32MP13
fix(st-crypto): improve RNG health test configuration
feat(st): add RNG minor version
feat(st-crypto): add multi instance and error management in RNG driver
feat(stm32mp2): add HASH and RNG compilation
feat(stm32mp25-fdts): add RNG node

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feat(mt8189): add UFS functions used by libbl31.a

Add UFS callback functions needed by the MediaTek's
private static library (libbl31.a).

Signed-off-by: Cloud Zhang <cloud.zhang@mediatek.corp-partn

feat(mt8189): add UFS functions used by libbl31.a

Add UFS callback functions needed by the MediaTek's
private static library (libbl31.a).

Signed-off-by: Cloud Zhang <cloud.zhang@mediatek.corp-partner.google.com>
Change-Id: I155b5a805a953e45f1a41a561f1d82f71b99541d

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feat(fvp): organize fvp_stmm_manifest.dts

To generalize manifest file for StandaloneMm for FVP,
organize this manifest file by separating:

* stmm_common.dtsi
- collection of macros to used by

feat(fvp): organize fvp_stmm_manifest.dts

To generalize manifest file for StandaloneMm for FVP,
organize this manifest file by separating:

* stmm_common.dtsi
- collection of macros to used by {plat_}stmm_*.dts(i) files.

* stmm_dev_region.dtsi
- device region template for StandaloneMm.
- If some environment don't required it, it can be excluded in
by not defining STMM_XXX macro.

* stmm_mem_region.dtsi
- memory region template for StandaloneMm.

* stmm_template.dts
- StandaloneMm manifest template defining common root node
information.

* fvp_stmm_{xxx}_manifest.dts
- Main StandaloneMm manifest file.
- According to environment, defines proper STMM_XXX value
to define device/memory region.
- device region can be excluded by not defining some STMM_XXX macro.

This is useful to define new StandaloneMm manifest
in different environments.

Change-Id: Ia9668c4994f589b178872d4d7a18a9f28075df74
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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feat(juno): add pseudo CRB area

To support StnadlaoneMm with fTPM, add pseudo CRB area used by fTPM.

Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
Change-Id: I8959faf0b222c326fefedf3f809cc96c276

feat(juno): add pseudo CRB area

To support StnadlaoneMm with fTPM, add pseudo CRB area used by fTPM.

Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
Change-Id: I8959faf0b222c326fefedf3f809cc96c276a769b

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feat(fvp): add pseudo CRB area

To support StandaloneMm with fTPM, add pseudo CRB area used by fTPM.

Change-Id: I43fd00dd23b0f4e6dbc8859808633a0c6051c8b6
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.

feat(fvp): add pseudo CRB area

To support StandaloneMm with fTPM, add pseudo CRB area used by fTPM.

Change-Id: I43fd00dd23b0f4e6dbc8859808633a0c6051c8b6
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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feat(juno): increase xtable for pseudo CRB

As normal pseudo CRB is allocated in DRAM1 area,
spmc running with SPMC_AT_EL3 need more subtable to map this area.
So, increase PLAT_SP_IMAGE_MAX_XLAT_TAB

feat(juno): increase xtable for pseudo CRB

As normal pseudo CRB is allocated in DRAM1 area,
spmc running with SPMC_AT_EL3 need more subtable to map this area.
So, increase PLAT_SP_IMAGE_MAX_XLAT_TABLES

Change-Id: I0a41b2f9ab127cc10c213fd1216a6fdd2e0ab850
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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feat(fvp): increase xtable for pseudo CRB for SPMC_AT_EL3

As normal pseudo CRB is allocated in DRAM1 area,
spmc running with SPMC_AT_EL3 need more subtable to map this area.
So, increase PLAT_SP_IMA

feat(fvp): increase xtable for pseudo CRB for SPMC_AT_EL3

As normal pseudo CRB is allocated in DRAM1 area,
spmc running with SPMC_AT_EL3 need more subtable to map this area.
So, increase PLAT_SP_IMAGE_MAX_XLAT_TABLES

Change-Id: I4c3cbf6242f2ccf154b93e9497ab9a21a4b67772
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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feat(fvp): tos_fw_config with transfer list

To load bl32's secure parition, tos_fw_config should be passed
via transfer list with DT_FFA_MANIFEST entry.

For this:
1. define PLAT_ARM_SPMC_SP_MANIF

feat(fvp): tos_fw_config with transfer list

To load bl32's secure parition, tos_fw_config should be passed
via transfer list with DT_FFA_MANIFEST entry.

For this:
1. define PLAT_ARM_SPMC_SP_MANIFEST_SIZE with PAGE_SIZE taken
from PLAT_ARM_HW_CONFIG_SIZE by reducing it as amount of
PLAT_ARM_SPMC_SP_MANIFEST_SIZE.

2. increase HAND_OFF transfer list size as much as
PLAT_ARM_SPMC_SP_MANIFEST_SIZE.

Change-Id: I56be7783ee4d257e33148f1f623a64bc498f1955
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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feat(arm): load tos_fw_cfg using xferlist in SPMC_AT_EL3

Load tos_fw_cfg when SPMC_AT_EL3 enabled and deliver its manifest
via transfer list and set its address in entrypoint's arg0 to load it
prope

feat(arm): load tos_fw_cfg using xferlist in SPMC_AT_EL3

Load tos_fw_cfg when SPMC_AT_EL3 enabled and deliver its manifest
via transfer list and set its address in entrypoint's arg0 to load it
properly by spmc_setup().

Change-Id: I43490d0bbe8288701efcce93313838395d41f330
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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feat(fvp): increase secure partition's table mapping count

For tpm event log event region passed to SP,
increase table mapping count.

Change-Id: Ie9f899a611b6715ea9a8bd3f532774d3f8f6955e
Signed-off

feat(fvp): increase secure partition's table mapping count

For tpm event log event region passed to SP,
increase table mapping count.

Change-Id: Ie9f899a611b6715ea9a8bd3f532774d3f8f6955e
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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feat(fvp): increase bl2 mmap tables for handoff

With firmware handoff and SPMC_AT_EL3, the BL2 translation tables
need to be one entry longer than they currently are.
Increase the current max length

feat(fvp): increase bl2 mmap tables for handoff

With firmware handoff and SPMC_AT_EL3, the BL2 translation tables
need to be one entry longer than they currently are.
Increase the current max length by this much to allow to
build these two configurations together.

Change-Id: Ifaeee5010143b53ba4f43c45011eaa8a28456bc5
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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feat(fvp): increase xtable for pseudo CRB for SPM_MM

As normal pseudo CRB is allocated in DRAM1 area,
spmc running with SPM_MM need more subtable to map this area.
So, increase PLAT_SP_IMAGE_MAX_XLA

feat(fvp): increase xtable for pseudo CRB for SPM_MM

As normal pseudo CRB is allocated in DRAM1 area,
spmc running with SPM_MM need more subtable to map this area.
So, increase PLAT_SP_IMAGE_MAX_XLAT_TABLES

Change-Id: If48e2eb90e3d4319b0588e4467f2bda0fbaf9a64
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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feat(juno): change PLAT_SP_IMAGE_NS_BUF_BASE

As PLAT_SP_IMAGE_NS_BUF_BASE is moved to NS_DRAM1 area [0],
PLAT_ARM_SP_IMAGE_STACK_BASE should be changed to
(PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE)

Li

feat(juno): change PLAT_SP_IMAGE_NS_BUF_BASE

As PLAT_SP_IMAGE_NS_BUF_BASE is moved to NS_DRAM1 area [0],
PLAT_ARM_SP_IMAGE_STACK_BASE should be changed to
(PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE)

Link: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/40336 [0]
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
Change-Id: I638fd7346853894d3377d63fc7fb4daf48415602

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feat(fvp): add extra DRAM configuration for TZC

As number of ARM_TZC_REGIONS_DEF is reduced by moving
PLAT_SP_IMAGE_NS_BUF_BASE into NS_DRAM1 area [0],
in SPM_MM or SPMC_AT_EL3, extra DRAM can be co

feat(fvp): add extra DRAM configuration for TZC

As number of ARM_TZC_REGIONS_DEF is reduced by moving
PLAT_SP_IMAGE_NS_BUF_BASE into NS_DRAM1 area [0],
in SPM_MM or SPMC_AT_EL3, extra DRAM can be configured in TZC.

Link: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/40336 [0]
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
Change-Id: I08e01016f0f4c534e08744117f36fb1fbd1b6e04

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feat(fvp): change PLAT_SP_IMAGE_NS_BUF_BASE

As PLAT_SP_IMAGE_NS_BUF_BASE is moved to NS_DRAM1 area [0],
PLAT_ARM_SP_IMAGE_STACK_BASE should be changed to
(PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE)

Lin

feat(fvp): change PLAT_SP_IMAGE_NS_BUF_BASE

As PLAT_SP_IMAGE_NS_BUF_BASE is moved to NS_DRAM1 area [0],
PLAT_ARM_SP_IMAGE_STACK_BASE should be changed to
(PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE)

Link: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/40336 [0]
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
Change-Id: Ic784dfcce921182968854a0fc90487754a8f59c8

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feat(neoverse-rd): change PLAT_SP_IMAGE_NS_BUF_BASE

As PLAT_SP_IMAGE_NS_BUF_BASE is moved to NS_DRAM1 area [0],
PLAT_ARM_SP_IMAGE_STACK_BASE should be changed to
(PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SI

feat(neoverse-rd): change PLAT_SP_IMAGE_NS_BUF_BASE

As PLAT_SP_IMAGE_NS_BUF_BASE is moved to NS_DRAM1 area [0],
PLAT_ARM_SP_IMAGE_STACK_BASE should be changed to
(PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE)

Link: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/40336 [0]
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
Change-Id: I421b1f1283600de81024c7415af9919c9afbe138

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feat(tc): change PLAT_SP_IMAGE_NS_BUF_BASE

As PLAT_SP_IMAGE_NS_BUF_BASE is moved to NS_DRAM1 area [0],
PLAT_ARM_SP_IMAGE_STACK_BASE should be changed to
(PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE)

Link

feat(tc): change PLAT_SP_IMAGE_NS_BUF_BASE

As PLAT_SP_IMAGE_NS_BUF_BASE is moved to NS_DRAM1 area [0],
PLAT_ARM_SP_IMAGE_STACK_BASE should be changed to
(PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE)

Link: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/40336 [0]
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
Change-Id: I6e97954a1ce91fdbda4edcdba5ccfa1d7c8ff475

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fix(intel): remove wfi polling when performing cpu on

Polling the WFI status produces vague result as
the secondary CPU will keep changing it's states.

Removing the polling WFI code as this will ca

fix(intel): remove wfi polling when performing cpu on

Polling the WFI status produces vague result as
the secondary CPU will keep changing it's states.

Removing the polling WFI code as this will cause
polling timeout since the CPU state is uncertain.

The CPU ON function will still work by removing this
check.

Change-Id: I1bb556a83ca16e122dfa35343de3e7cc39c5b678
Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): fix socfpga_psci for cpu on off function

Fix for CPU ON / OFF Function calling from Linux Kernel.

Change-Id: Ie450acf7e537ed60ef4b2e8d785e62d94e52482f
Signed-off-by: Boon Khai Ng <boon.

fix(intel): fix socfpga_psci for cpu on off function

Fix for CPU ON / OFF Function calling from Linux Kernel.

Change-Id: Ie450acf7e537ed60ef4b2e8d785e62d94e52482f
Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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Merge changes from topic "ar/soc_name" into integration

* changes:
feat(fvp): add SoC name support to FVP
feat(smccc): add SoC name support to SMCCC_ARCH_SOC_ID

Merge "feat(juno): support StandaloneMm" into integration