| f1b1fae9 | 17-Jun-2025 |
Jit Loon Lim <jit.loon.lim@altera.com> |
fix(intel): iossm v2 enhancement refactor
This patch is to used to update iossm v2 enhancement. The major change is to replace io_mb_req to mmio_read. Next is to refactor the code.
Change-Id: Id084
fix(intel): iossm v2 enhancement refactor
This patch is to used to update iossm v2 enhancement. The major change is to replace io_mb_req to mmio_read. Next is to refactor the code.
Change-Id: Id0842392f362e30252f1ac9f32797d8d3a419997 Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>
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| 30bbc4fa | 14-Aug-2025 |
Boyan Karatotev <boyan.karatotev@arm.com> |
fix(drtm): remove plat_system_reset()
The name plat_system_reset() has been in use for some time by a mediatek platform (in plat/mediatek/mt8173/plat_pm.c). However, DRTM added a global hook, that i
fix(drtm): remove plat_system_reset()
The name plat_system_reset() has been in use for some time by a mediatek platform (in plat/mediatek/mt8173/plat_pm.c). However, DRTM added a global hook, that is only implemented on FVP, that conflicts with it. This sometimes results in failed builds.
DRTM remediation ends with a platform reset. However, there is currently an error message printed that this is not supported. In this case, the correct thing to do is to panic and as such this hook is not needed.
Further, the correct sequence to reset the system is different and is only fully implemented by psci_system_reset(). This is a portable implementation supported by a wide variety of platform.
So remove plat_system_reset(). Once DRTM remediation properly supports resetting, the psci_system_reset() function should be used to achieve reset correctly and portably.
Change-Id: Ia4e150c51aeec613838464fbb0e1d0542f19ccab Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
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| 13630966 | 23-May-2025 |
Mahesh Rao <mahesh.rao@altera.com> |
fix(intel): add missing cache flush operation for hmac
Add missing cache flush operation for HMAC verify operation.Also update the code to query the correct buffer for the final result of HMAC veri
fix(intel): add missing cache flush operation for hmac
Add missing cache flush operation for HMAC verify operation.Also update the code to query the correct buffer for the final result of HMAC verify operation.
Change-Id: I85208765313b9048cfef13727d280dca8af6d548 Signed-off-by: Mahesh Rao <mahesh.rao@altera.com> Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>
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| 60a15d63 | 19-Aug-2025 |
Mark Dykes <mark.dykes@arm.com> |
Merge "fix(intel): select the DFI interface based on the hand-off data" into integration |
| ab5cbea6 | 19-Aug-2025 |
Mark Dykes <mark.dykes@arm.com> |
Merge "fix(intel): set BIT2 of system manager MPFE Interface Select" into integration |
| 6d36b699 | 19-Aug-2025 |
Mark Dykes <mark.dykes@arm.com> |
Merge "fix(intel): flush the mailbox response buffer in SiPSVC V3" into integration |
| b3555f12 | 14-Aug-2025 |
Prasad Kummari <prasad.kummari@amd.com> |
fix(versal2): runtime console in debug mode
Whenever DEBUG is set to 1, the Makefile forces CONSOLE_RUNTIME to pl011, regardless of the user-specified CONSOLE value. This causes a build requested wi
fix(versal2): runtime console in debug mode
Whenever DEBUG is set to 1, the Makefile forces CONSOLE_RUNTIME to pl011, regardless of the user-specified CONSOLE value. This causes a build requested with CONSOLE=pl011_1 to register both pl011_1 and pl011 as boot and runtime consoles. If the hardware is connected only to UART1, this causes TF-A to hang when UART0 is selected as the runtime console, since it waits indefinitely on the transmit FIFO. The fix ensures that, in a DEBUG build, CONSOLE_RUNTIME defaults to the same value as CONSOLE.
Change-Id: I2e29d5b77c43aa65f58224d226683f4a8d94271a Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
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| 18283e6d | 14-Aug-2025 |
Prasad Kummari <prasad.kummari@amd.com> |
fix(versal-net): runtime console in debug mode
Whenever DEBUG is set to 1, the Makefile forces CONSOLE_RUNTIME to pl011, regardless of the user-specified VERSAL_NET_CONSOLE value. This causes a buil
fix(versal-net): runtime console in debug mode
Whenever DEBUG is set to 1, the Makefile forces CONSOLE_RUNTIME to pl011, regardless of the user-specified VERSAL_NET_CONSOLE value. This causes a build requested with VERSAL_NET_CONSOLE=pl011_1 to register both pl011_1 and pl011 as boot and runtime consoles. If the hardware is connected only to UART1, this causes TF-A to hang when UART0 is selected as the runtime console, since it waits indefinitely on the transmit FIFO. The fix ensures that, in a DEBUG build, CONSOLE_RUNTIME defaults to the same value as VERSAL_NET_CONSOLE.
Change-Id: Icad043a61f9d90480a8aceab701a5791d26e3d70 Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
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| 0701792f | 12-Aug-2025 |
Prasad Kummari <prasad.kummari@amd.com> |
fix(versal): runtime console in debug mode
Whenever DEBUG is set to 1, the Makefile forces CONSOLE_RUNTIME to pl011, regardless of the user-specified VERSAL_CONSOLE value. This causes a build reques
fix(versal): runtime console in debug mode
Whenever DEBUG is set to 1, the Makefile forces CONSOLE_RUNTIME to pl011, regardless of the user-specified VERSAL_CONSOLE value. This causes a build requested with VERSAL_CONSOLE=pl011_1 to register both pl011_1 and pl011 as boot and runtime consoles. If the hardware is connected only to UART1, this causes TF-A to hang when UART0 is selected as the runtime console, since it waits indefinitely on the transmit FIFO. The fix ensures that, in a DEBUG build, CONSOLE_RUNTIME defaults to the same value as VERSAL_CONSOLE.
Change-Id: I7aeedb04040ea4ab4b8aecde98af5cc39df09c1a Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
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| 25463503 | 14-Aug-2025 |
Prasad Kummari <prasad.kummari@amd.com> |
fix(zynqmp): runtime console in debug mode
Whenever DEBUG is set to 1, the Makefile forces CONSOLE_RUNTIME to cadence1, regardless of the user-specified ZYNQMP_CONSOLE value. This causes a build req
fix(zynqmp): runtime console in debug mode
Whenever DEBUG is set to 1, the Makefile forces CONSOLE_RUNTIME to cadence1, regardless of the user-specified ZYNQMP_CONSOLE value. This causes a build requested with ZYNQMP_CONSOLE= cadence1 to register both cadence1 and cadence as boot and runtime consoles. If the hardware is connected only to UART1, this causes TF-A to hang when UART0 is selected as the runtime console, since it waits indefinitely on the transmit FIFO. The fix ensures that, in a DEBUG build, CONSOLE_RUNTIME defaults to the same value as ZYNQMP_CONSOLE.
Change-Id: Ieff6adf4c6c30e07b8c7309c4835dcb32dcf9373 Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
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| b37872f5 | 19-Aug-2025 |
Govindraj Raja <govindraj.raja@arm.com> |
Merge "feat(juno): increase MAX_XLAT_TABLES for SPMC_AT_EL3" into integration |
| 3b9411f3 | 19-Aug-2025 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "fix(bl31): remove incorrect asserts" into integration |
| 3da2d29c | 18-Jul-2025 |
Raymond Sun <raymond.sun@mediatek.com> |
feat(mt8189): add thermal driver support
The thermal sensor will be turned off when the system is in suspend state. This patch adds support for the suspend/resume flow for the thermal sensor.
Signe
feat(mt8189): add thermal driver support
The thermal sensor will be turned off when the system is in suspend state. This patch adds support for the suspend/resume flow for the thermal sensor.
Signed-off-by: Raymond Sun <raymond.sun@mediatek.com> Change-Id: I930574497b232627e0ca8f45701aead4e785c363
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| ea7d633a | 18-Aug-2025 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "fix(imx8m): don't reconfigure default region0" into integration |
| 64e58ce3 | 12-Jun-2025 |
Dhruva Gole <d-gole@ti.com> |
fix(ti): specify allowable rcv_addr in mailbox
The ti_sci_transport_recv function had an overly restrictive check where we enforced the rcv_addr to be always at the start of the RX_START region in s
fix(ti): specify allowable rcv_addr in mailbox
The ti_sci_transport_recv function had an overly restrictive check where we enforced the rcv_addr to be always at the start of the RX_START region in shared memory. This started failing unnecessarily when messages started being received at a location other than the beginning. However, the sender might send the messages at any location within the share memory region if it does some sort of buffer management. In such a case, TFA needs to just make sure the message being read is well within the allocated shared memory region. Not necessarily at the start.
Fixes: 9347ff4561e445d4 ("feat(ti): add support for TI mailbox driver") Change-Id: I32cf0f5e4b9fedf49e40ace0bef06b7fc4c016f6 Signed-off-by: Dhruva Gole <d-gole@ti.com>
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| 618e37c3 | 30-Mar-2025 |
Saivardhan Thatikonda <saivardhan.thatikonda@amd.com> |
fix(common): add missing curly braces
This corrects the MISRA violation C2012-15.6: The body of an iteration-statement or a selection-statement shall be a compound-statement.Enclosed statement body
fix(common): add missing curly braces
This corrects the MISRA violation C2012-15.6: The body of an iteration-statement or a selection-statement shall be a compound-statement.Enclosed statement body within the curly braces.
Change-Id: I24a73929c589e67f9ef9ef6d756d5c451a8b9219 Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>
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| 4249a4fb | 28-Nov-2023 |
Jacky Bai <ping.bai@nxp.com> |
feat(imx94): add initial support for imx94
add the initial support for i.MX94.
Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com> Reviewe
feat(imx94): add initial support for imx94
add the initial support for i.MX94.
Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Change-Id: I1f196a4b27d8f67c65be840b92e2d5d5467df546
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| 7bde9a4e | 25-Jan-2024 |
Sahil Malhotra <sahil.malhotra@nxp.com> |
feat(imx95): add optee support
Add OP-TEE support for i.MX95
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com> Change-Id: I5babfb805bcdb8c0538d546859a9788e5a068d40 |
| b182f709 | 01-Dec-2023 |
Ji Luo <ji.luo@nxp.com> |
feat(imx95): support trusty os
Add configs to support Trusty OS on i.MX 95.
Signed-off-by: Ji Luo <ji.luo@nxp.com> Change-Id: I14f0cb20700a5f9df9b83f54add1e8af92b23523 |
| f7e7ea1f | 22-Aug-2024 |
Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com> |
feat(imx95): implement a semaphore for GIC quiescing
As there is no way to reset the GIC on iMX95, SM(System Controller) needs to quiesce the GIC using the GIC waker. But AP can also be touching GIC
feat(imx95): implement a semaphore for GIC quiescing
As there is no way to reset the GIC on iMX95, SM(System Controller) needs to quiesce the GIC using the GIC waker. But AP can also be touching GIC waker register during entry/exit from low power modes. Add a semaphore to provide a critical section for GIC waker. The last two words in the TF-A MU 1K SRAM space is used to hold the semaphore (follow the Peterson'salgorithm for mutual exclusion).
Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: Ic5d696ac83668e72d9c3204d7ec047ac9f751e94
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| d70b09f8 | 22-Sep-2022 |
Peng Fan <peng.fan@nxp.com> |
feat(imx95): add initial support for i.MX95
Add support platform i.MX95. The System Manager running on M33 manages system critical resources, so ATF needs communicate with System Manager. This patch
feat(imx95): add initial support for i.MX95
Add support platform i.MX95. The System Manager running on M33 manages system critical resources, so ATF needs communicate with System Manager. This patch is to add the basic support for i.MX95.
Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: I10c0cc309ec90ba7b5a30d000644f75c2e5b7b19
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| 11684655 | 07-Nov-2023 |
Jacky Bai <ping.bai@nxp.com> |
feat(imx9): add necessary ele api call support
Add the soc info and release xspi gmid ELE API call support.
Also add soc id sip call support. we need to flush the soc info buffer address range to m
feat(imx9): add necessary ele api call support
Add the soc info and release xspi gmid ELE API call support.
Also add soc id sip call support. we need to flush the soc info buffer address range to make sure no stolen data in the cache as the ELE will fill the data without coherance support.
Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: I3d486902960fe39bdfe810f0d0c8ee75bae6fcc5
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| 4ddfb6f1 | 28-Aug-2024 |
Jacky Bai <ping.bai@nxp.com> |
feat(imx9): add imx9 common code base
Add the basic common code that will be reused for SCMI based i.MX9 platform.
Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: I79b56822db20f2b41723783483
feat(imx9): add imx9 common code base
Add the basic common code that will be reused for SCMI based i.MX9 platform.
Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: I79b56822db20f2b41723783483db263d2e439562
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| 7c0f67a1 | 18-Jun-2025 |
Jacky Bai <ping.bai@nxp.com> |
refactor(imx): drop the __dead2 attribute
Drop the __dead2 attribute to make sure these functions can be implemented as no dead.
Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: I93129cdc6dae
refactor(imx): drop the __dead2 attribute
Drop the __dead2 attribute to make sure these functions can be implemented as no dead.
Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: I93129cdc6daea494ac5dd6868a05d97eaf1a610c
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| c7294df9 | 26-Jun-2025 |
Jacky Bai <ping.bai@nxp.com> |
fix(imx): add static attribute for platform specific gic struct
Add 'static' attribute for platform specific gic struct define to allow us to use the generic gic driver for i.MX9 platform.
Signed-o
fix(imx): add static attribute for platform specific gic struct
Add 'static' attribute for platform specific gic struct define to allow us to use the generic gic driver for i.MX9 platform.
Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: I34977138f23cdd9c736e816b14200c3ca502d8de
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