| 000e25bf | 07-Aug-2022 |
Joanna Farley <joanna.farley@arm.com> |
Merge "fix(versal): use only one space for indentation" into integration |
| 0da574c1 | 07-Aug-2022 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes from topic "xilinx-versal-coding-style" into integration
* changes:
fix(versal): fix code indentation issues
fix(versal): fix macro coding style issues |
| dee58859 | 04-Aug-2022 |
Michal Simek <michal.simek@amd.com> |
fix(versal): use only one space for indentation
Trivial patch to remove additional space.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: Ifa33dee81243c0b21ca0f13b8e4d575646818162 |
| e95abc4c | 14-Jul-2022 |
Salome Thirot <salome.thirot@arm.com> |
fix: make TF-A use provided OpenSSL binary
Currently Tf-A uses whatever openssl binary is on the system to sign
images. However if OPENSSL_DIR is specified in the build flags this can
lead to linkin
fix: make TF-A use provided OpenSSL binary
Currently Tf-A uses whatever openssl binary is on the system to sign
images. However if OPENSSL_DIR is specified in the build flags this can
lead to linking issues as the system binary can end up being linked
against shared libraries provided in OPENSSL_DIR/lib if both binaries
(the system's and the on in OPENSSL_DIR/bin) are the same version.
This patch ensures that the binary used is always the one given by
OPENSSL_DIR to avoid those link issues.
Signed-off-by: Salome Thirot <salome.thirot@arm.com>
Change-Id: Ib534e06ebc8482e4391e376d3791a87968de4a99
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|
| 72583f92 | 29-Jul-2022 |
Michal Simek <michal.simek@amd.com> |
fix(versal): fix code indentation issues
Next line should be aligned with the previous code.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I20d82ba5fa70fa252341b62e57fac265241f3391 |
| 80806aa1 | 27-Jul-2022 |
Michal Simek <michal.simek@amd.com> |
fix(versal): fix macro coding style issues
Use only one space between #define and macro name.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: Ieb9bdd5bcfa56bd265df72692a09c7340fe132cb |
| 17e76b5e | 02-Aug-2022 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge "feat(plat/qti): fix to support cpu errata" into integration |
| c1522768 | 01-Aug-2022 |
Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
Merge changes from topic "st_fip_uuid" into integration
* changes:
feat(stm32mp1): retrieve FIP partition by type UUID
feat(guid-partition): allow to find partition by type UUID
refactor(stm32
Merge changes from topic "st_fip_uuid" into integration
* changes:
feat(stm32mp1): retrieve FIP partition by type UUID
feat(guid-partition): allow to find partition by type UUID
refactor(stm32mp1): update PLAT_PARTITION_MAX_ENTRIES
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|
| 342a65fb | 01-Aug-2022 |
Joanna Farley <joanna.farley@arm.com> |
Merge "feat(zynqmp): protect eFuses from non-secure access" into integration |
| 19f92c4c | 31-Jul-2022 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
fix(versal): resolve misra 10.1 warnings
MISRA Violation: MISRA-C: 2012 R.10.1
-The operand to the operator does not have an essentially
unsigned type.
Signed-off-by: Venkatesh Yadav Abbarapu <venk
fix(versal): resolve misra 10.1 warnings
MISRA Violation: MISRA-C: 2012 R.10.1
-The operand to the operator does not have an essentially
unsigned type.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I4873a620086dfd6f636fe730165a9d13a29e9652
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|
| f7c48d9e | 31-Jul-2022 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
fix(versal): resolve the misra 4.6 warnings
MISRA Violation: MISRA-C:2012 R.4.6
- Using basic numerical type int rather than a typedef
that includes size and signedness information.
Signed-off-by:
fix(versal): resolve the misra 4.6 warnings
MISRA Violation: MISRA-C:2012 R.4.6
- Using basic numerical type int rather than a typedef
that includes size and signedness information.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: Ieff90b5311a3bde8a2cb302ca81c23eeee6d235a
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|
| d0b7286e | 29-Apr-2022 |
Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com> |
feat(zynqmp): protect eFuses from non-secure access
When configuration option ZYNQMP_SECURE_EFUSES is defined then Xilinx
ZynqMP's PS eFuses can only be accesses from secure state.
This enables eFu
feat(zynqmp): protect eFuses from non-secure access
When configuration option ZYNQMP_SECURE_EFUSES is defined then Xilinx
ZynqMP's PS eFuses can only be accesses from secure state.
This enables eFuses to be reserved and protected only for security use
cases for example in OP-TEE.
Change-Id: I866905e35ce488f50f5f6e1b4667b08a9fa2386d
Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
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|
| 6cc743cf | 04-Apr-2022 |
Saurabh Gorecha <quic_sgorecha@quicinc.com> |
feat(plat/qti): fix to support cpu errata
fix to support ARM CPU errata based on core used.
Signed-off-by: Saurabh Gorecha <quic_sgorecha@quicinc.com>
Change-Id: If1a438f98f743435a7a0b683a32ccf1416
feat(plat/qti): fix to support cpu errata
fix to support ARM CPU errata based on core used.
Signed-off-by: Saurabh Gorecha <quic_sgorecha@quicinc.com>
Change-Id: If1a438f98f743435a7a0b683a32ccf14164db37e
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|
| bfc514f1 | 28-Jul-2022 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
fix(xilinx): miscellaneous fixes for xilinx platforms
This patch gathers miscellaneous minor fixes to the xilinx
platforms like tabs for indentation and misra 10.1 warnings.
Signed-off-by: Michal S
fix(xilinx): miscellaneous fixes for xilinx platforms
This patch gathers miscellaneous minor fixes to the xilinx
platforms like tabs for indentation and misra 10.1 warnings.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I4cdb89ffec7d5abc64e065ed5b5e5d10b30ab9f9
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|
| 9090fe00 | 20-Jun-2022 |
Vishnu Banavath <vishnu.banavath@arm.com> |
(feat)n1sdp: add support for OP-TEE SPMC
These changes are to add support for loading and booting
OP-TEE as SPMC running at SEL1 for N1SDP platform.
Signed-off-by: Vishnu Banavath <vishnu.banavath@
(feat)n1sdp: add support for OP-TEE SPMC
These changes are to add support for loading and booting
OP-TEE as SPMC running at SEL1 for N1SDP platform.
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
Change-Id: I0514db646d4868b6f0c56f1ea60495cb3f7364fd
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|
| 09acc421 | 25-Jul-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "feat(tc): introduce TC2 platform" into integration |
| 47f81453 | 21-Jul-2022 |
Michal Simek <michal.simek@amd.com> |
fix(versal): remove clock related macros
TF-A doesn't configure clock on Versal. Setup is done by previous
bootloader (called PLM) that's why there is no need to have macro listed in
headers. Also p
fix(versal): remove clock related macros
TF-A doesn't configure clock on Versal. Setup is done by previous
bootloader (called PLM) that's why there is no need to have macro listed in
headers. Also previous phase can disable access to these registers that's
why better to remove them.
Change-Id: I53ba344ad932c532b0babdce9d2b26e4c2c1b846
Signed-off-by: Michal Simek <michal.simek@amd.com>
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|
| eebd2c3f | 04-Apr-2022 |
Rupinderjit Singh <rupinderjit.singh@arm.com> |
feat(tc): introduce TC2 platform
Added a platform support to use tc2 specific CPU cores.
Signed-off-by: Rupinderjit Singh <rupinderjit.singh@arm.com>
Change-Id: Ib76d440e358e9bd1cf80aec5b8591f7a6e4
feat(tc): introduce TC2 platform
Added a platform support to use tc2 specific CPU cores.
Signed-off-by: Rupinderjit Singh <rupinderjit.singh@arm.com>
Change-Id: Ib76d440e358e9bd1cf80aec5b8591f7a6e47ecbd
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|
| 8597a8cb | 20-Jul-2022 |
Olivier Deprez <olivier.deprez@arm.com> |
fix(tc): tc2 bl1 start address shifted by one page
Change [1] is specific to TC2 model and breaks former TC0/TC1 test
configs.
BL1 start address is 0x0 on TC0/TC1 and 0x1000 from TC2 onwards.
Fix by
fix(tc): tc2 bl1 start address shifted by one page
Change [1] is specific to TC2 model and breaks former TC0/TC1 test
configs.
BL1 start address is 0x0 on TC0/TC1 and 0x1000 from TC2 onwards.
Fix by adding conditional defines depending on TARGET_PLATFORM build
flag.
[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/15917
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I51f77e6a61ca8eaa6871c19cabe9deb1288f5a9d
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|
| b86e1aad | 20-Jul-2022 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
feat(versal): resolve the misra 10.1 warnings
MISRA Violation: MISRA-C:2012 R.10.1
-The operand to the operator does not have an essentially unsigned type.
Signed-off-by: Venkatesh Yadav Abbarapu <
feat(versal): resolve the misra 10.1 warnings
MISRA Violation: MISRA-C:2012 R.10.1
-The operand to the operator does not have an essentially unsigned type.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I9cde2f1ebceaad8a41c69489ef1d2e6f21f04ed1
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|
| 41bdb475 | 19-Jul-2022 |
Joanna Farley <joanna.farley@arm.com> |
Merge "feat(versal): get the handoff params using IPI" into integration |
| e5daf0a5 | 19-Jul-2022 |
Joanna Farley <joanna.farley@arm.com> |
Merge "refactor(xilinx): move the atf handoff structure" into integration |
| e82d990b | 19-Jul-2022 |
Joanna Farley <joanna.farley@arm.com> |
Merge "refactor(versal): move payload and module ID macros" into integration |
| 2a2b51d8 | 08-Jul-2022 |
Yidi Lin <yidilin@chromium.org> |
fix(mt8186): move SSPM base register definition to platform_def.h
- move base register definition to platform_def.h for maintenance.
- SSPM_MBOX_3_BASE is redefined, use SSPM_MBOX_BASE instead.
Sig
fix(mt8186): move SSPM base register definition to platform_def.h
- move base register definition to platform_def.h for maintenance.
- SSPM_MBOX_3_BASE is redefined, use SSPM_MBOX_BASE instead.
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Change-Id: Ibb0291ce7b7426068392e90bd70f29d1a90d5297
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|
| 37d87416 | 18-Jul-2022 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "refactor(fvp): add missing header guard in fvp_critical_data.h" into integration |