fix(zynqmp): move bl31 with DEBUG=1 back to OCM

By default placing bl31 to addrexx 0x1000 is not good. Because this
location is used by U-Boot SPL. That's why move TF-A back to OCM where it
should b

fix(zynqmp): move bl31 with DEBUG=1 back to OCM

By default placing bl31 to addrexx 0x1000 is not good. Because this
location is used by U-Boot SPL. That's why move TF-A back to OCM where it
should be placed. BL31_BASE address exactly matches which requested address
for U-BOOT SPL boot flow.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I608c1b88baffec538c6ae528f057820e34971c4c

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feat(arm): retrieve the right ROTPK for cca

The cca chain of trust involves 3 root-of-trust public keys:
- The CCA components ROTPK.
- The platform owner ROTPK (PROTPK).
- The secure world ROTPK (SW

feat(arm): retrieve the right ROTPK for cca

The cca chain of trust involves 3 root-of-trust public keys:
- The CCA components ROTPK.
- The platform owner ROTPK (PROTPK).
- The secure world ROTPK (SWD_ROTPK).

Use the cookie argument as a key ID for plat_get_rotpk_info() to return
the appropriate one.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Ieaae5b0bc4384dd12d0b616596596b031179044a

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feat(arm): add support for cca CoT

- Use the development PROTPK and SWD_ROTPK if using cca CoT.

- Define a cca CoT build flag for the platform code to provide
different implementations where needed

feat(arm): add support for cca CoT

- Use the development PROTPK and SWD_ROTPK if using cca CoT.

- Define a cca CoT build flag for the platform code to provide
different implementations where needed.

- When ENABLE_RME=1, CCA CoT is selected by default on Arm
platforms if no specific CoT is specified by the user.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I70ae6382334a58d3c726b89c7961663eb8571a64

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feat(arm): provide some swd rotpk files

When using the new cca chain of trust, a new root of trust key is needed
to authenticate the images belonging to the secure world. Provide a
development one t

feat(arm): provide some swd rotpk files

When using the new cca chain of trust, a new root of trust key is needed
to authenticate the images belonging to the secure world. Provide a
development one to deploy this on Arm platforms.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I9ea7bc1c15c0c94c1021d879a839cef40ba397e3

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refactor(arm): add cca CoT certificates to fconf

Adding support in fconf for the cca CoT certificates for cca, core_swd,
and plat key.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

refactor(arm): add cca CoT certificates to fconf

Adding support in fconf for the cca CoT certificates for cca, core_swd,
and plat key.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I8019cbcb7ccd4de6da624aebf3611b429fb53f96

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refactor(fvp): increase bl2 size when bl31 in DRAM

Increase the space for BL2 by 0xC000 to accommodate the increase in size
of BL2 when ARM_BL31_IN_DRAM is set.

Signed-off-by: Lauren Wehrmeister <l

refactor(fvp): increase bl2 size when bl31 in DRAM

Increase the space for BL2 by 0xC000 to accommodate the increase in size
of BL2 when ARM_BL31_IN_DRAM is set.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Ifc99da51f2de3c152bbed1c8269dcc8b9100797a

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Merge "feat(zynqmp): add support for xck24 silicon" into integration

Merge changes from topic "stm32mp-emmc-boot-fip" into integration

* changes:
feat(stm32mp1): extend STM32MP_EMMC_BOOT support to FIP format
refactor(mmc): replace magic value with new PART_CFG_B

Merge changes from topic "stm32mp-emmc-boot-fip" into integration

* changes:
feat(stm32mp1): extend STM32MP_EMMC_BOOT support to FIP format
refactor(mmc): replace magic value with new PART_CFG_BOOT_PARTITION_NO_ACCESS
refactor(mmc): export user/boot partition switch functions

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feat(st): search pinctrl node by compatible

Instead of searching pinctrl node with its name, search with its
compatible. This will be necessary before pin-controller name changes
to pinctrl due to k

feat(st): search pinctrl node by compatible

Instead of searching pinctrl node with its name, search with its
compatible. This will be necessary before pin-controller name changes
to pinctrl due to kernel yaml changes.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I00590414fa65e193c6a72941a372bcecac673f60

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feat(zynqmp): add support for xck24 silicon

Add support for new xck24 device.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilin

feat(zynqmp): add support for xck24 silicon

Add support for new xck24 device.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I913a34d5a48ea665aaa4348f573fc59566dd5a9b

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Merge "feat(imx8mq): add 100us delay after USB OTG SRC bit 0 clear" into integration

Merge "fix(imx8mq): correct architected counter frequency" into integration

fix(zynqmp): resolve the misra 8.6 warnings

MISRA Violation: MISRA-C:2012 R.8.6
- Function is declared but never defined.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Cha

fix(zynqmp): resolve the misra 8.6 warnings

MISRA Violation: MISRA-C:2012 R.8.6
- Function is declared but never defined.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I0df53ef4b2c91fa8ec3bf3e5491bf37dd7400685

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fix(zynqmp): resolve the misra 4.6 warnings

MISRA Violation: MISRA-C:2012 R.4.6
- Using basic numerical type int rather than a typedef
that includes size and signedness information.

Signed-off-by:

fix(zynqmp): resolve the misra 4.6 warnings

MISRA Violation: MISRA-C:2012 R.4.6
- Using basic numerical type int rather than a typedef
that includes size and signedness information.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I9fb686e7aa2b85af6dfcb7bb5f87eddf469fb85c

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Merge "fix(plat/zynqmp): fix coverity scan warnings" into integration

feat(stm32mp1): extend STM32MP_EMMC_BOOT support to FIP format

STM32MP_EMMC_BOOT allowed placing SSBL into the eMMC boot
partition along with FSBL. This allows atomic update of both
FSBL and SSBL at

feat(stm32mp1): extend STM32MP_EMMC_BOOT support to FIP format

STM32MP_EMMC_BOOT allowed placing SSBL into the eMMC boot
partition along with FSBL. This allows atomic update of both
FSBL and SSBL at the same time. Previously, this was only
possible for the FSBL, as the eMMC layout expected by TF-A
had a single SSBL GPT partition in the eMMC user area.
TEE binaries remained in dedicated GPT partitions whether
STM32MP_EMMC_BOOT was on or off.

The new FIP format collects SSBL and TEE partitions into
a single binary placed into a GPT partition.
Extend STM32MP_EMMC_BOOT, so eMMC-booted TF-A first uses
a FIP image placed at offset 256K into the active eMMC boot
partition. If no FIP magic is detected at that offset or if
STM32MP_EMMC_BOOT is disabled, the GPT on the eMMC user area
will be consulted as before.

This allows power fail-safe update of all firmware using the
built-in eMMC boot selector mechanism, provided it fits into
the boot partition - SZ_256K. SZ_256K was chosen because it's
the same offset used with the legacy format and because it's
the size of the on-chip SRAM, where the STM32MP15x BootROM
loads TF-A into. As such, TF-A may not exceed this size limit
for existing SoCs.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Change-Id: Id7bec45652b3a289ca632d38d4b51316c5efdf8d

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fix(measured-boot): add SP entries to event_log_metadata

Add SP entries to event_log_metadata if SPD_spmd is enabled. Otherwise
the platform cannot boot with measured boot enabled.

Signed-off-by: I

fix(measured-boot): add SP entries to event_log_metadata

Add SP entries to event_log_metadata if SPD_spmd is enabled. Otherwise
the platform cannot boot with measured boot enabled.

Signed-off-by: Imre Kis <imre.kis@arm.com>
Change-Id: I525eb50e7bb60796b63a8c7f81962983017bbf87

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fix(versal): resolve misra 15.6 warnings

MISRA Violation: MISRA-C:2012 R.15.6
- The body of an iteration-statement or a selection-statement shall be
a compound statement.

Signed-off-by: Venkatesh Y

fix(versal): resolve misra 15.6 warnings

MISRA Violation: MISRA-C:2012 R.15.6
- The body of an iteration-statement or a selection-statement shall be
a compound statement.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: Ia1d6fcabd36d18ff2dab6c22579ffafd5211fc1f

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feat(imx8mq): add 100us delay after USB OTG SRC bit 0 clear

After the SRC bit clear, we must wait for a while to make sure
the operation is finished. And don't enable all the PU domains
by default.

feat(imx8mq): add 100us delay after USB OTG SRC bit 0 clear

After the SRC bit clear, we must wait for a while to make sure
the operation is finished. And don't enable all the PU domains
by default.

for USB OTG, the limitations are:
1. before system clock configuration. ipg clock runs at 12.5MHz.
delay time should longer than 82us.

2. after system clock configuration. ipg clock runs at 66.5MHz.
delay time should longer than 15.3us.

so add udelay 100 to safely clear the SRC bit 0.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I52e8e7739fdaaf86442bcd148e768b6af38bcdb7

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fix(zynqmp): resolve misra 8.13 warnings

MISRA Violation: MISRA-C:2012 R.8.13
- The pointer variable points to a non-constant type
but does not modify the object it points to. Consider
adding const

fix(zynqmp): resolve misra 8.13 warnings

MISRA Violation: MISRA-C:2012 R.8.13
- The pointer variable points to a non-constant type
but does not modify the object it points to. Consider
adding const qualifier to the points-to type.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: Ifd06c789cfd3babe1f5c0a17aff1ce8e70c87b05

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fix(versal): resolve misra 8.13 warnings

MISRA Violation: MISRA-C:2012 R.8.13
- The pointer variable points to a non-constant type
but does not modify the object it points to. Consider
adding const

fix(versal): resolve misra 8.13 warnings

MISRA Violation: MISRA-C:2012 R.8.13
- The pointer variable points to a non-constant type
but does not modify the object it points to. Consider
adding const qualifier to the points-to type.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I74e1b69290e081645bec8bb380128936190b5e24

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fix(versal): resolve the misra 4.6 warnings

MISRA Violation: MISRA-C:2012 R.4.6
- Using basic numerical type int rather than a typedef
that includes size and signedness information.

Signed-off-by:

fix(versal): resolve the misra 4.6 warnings

MISRA Violation: MISRA-C:2012 R.4.6
- Using basic numerical type int rather than a typedef
that includes size and signedness information.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I4eccce7e238f283348a5013e2e45c91435b4ae4e

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fix(imx8mq): correct architected counter frequency

Different from other i.MX SoCs, which typically use a 24MHz reference clock,
the i.MX8MQ uses a 25MHz reference clock. As the architected timer clo

fix(imx8mq): correct architected counter frequency

Different from other i.MX SoCs, which typically use a 24MHz reference clock,
the i.MX8MQ uses a 25MHz reference clock. As the architected timer clock
frequency is directly sourced from the reference clock via a /3 divider this
SoC runs the timers at 8.33MHz.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Change-Id: Ief36af9ffebce7cb75a200124134828d3963e744

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feat(plat/xilinx/zynqmp): optimization on pinctrl_functions

Optimizing the pinctrl_functions structure. Remove the pointer to
array of u16 type which consumes a lot of memory (64bits pointer to
arra

feat(plat/xilinx/zynqmp): optimization on pinctrl_functions

Optimizing the pinctrl_functions structure. Remove the pointer to
array of u16 type which consumes a lot of memory (64bits pointer to
array + 16B for END_OF_GROUPS + almost useless 8bits on every entry
which is the same for every group) and add two new members of type
u16 and u8 with the name called group_base and group_size
respectively.

The group_base member contains the base value of pinctrl group whereas
the group_size member contains the total number of groups requested
from the pinctrl function.

Overall, it saves around ~2KB of RAM and ~0.7KB of code memory.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Ronak Jain <ronak.jain@xilinx.com>
Change-Id: I79b761b45df350d390fa344d411b340d9b2f13ac

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Merge changes from topic "ffa_el3_spmc" into integration

* changes:
feat(fvp): add plat hook for memory transactions
feat(spmc): enable handling of the NS bit
feat(spmc): add support for v1.1

Merge changes from topic "ffa_el3_spmc" into integration

* changes:
feat(fvp): add plat hook for memory transactions
feat(spmc): enable handling of the NS bit
feat(spmc): add support for v1.1 FF-A memory data structures
feat(spmc/mem): prevent duplicated sharing of memory regions
feat(spmc/mem): support multiple endpoints in memory transactions
feat(spmc): add support for v1.1 FF-A boot protocol
feat(plat/fvp): introduce accessor function to obtain datastore
feat(spmc/mem): add FF-A memory management code

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