| de310e1e | 07-Jul-2022 |
Rex-BC Chen <rex-bc.chen@mediatek.com> |
feat(mt8188): initialize platform for MediaTek MT8188
- Add basic platform setup.
- Add MT8188 documentation at docs/plat/.
- Add generic CPU helper functions.
- Add basic register address.
- Add mt
feat(mt8188): initialize platform for MediaTek MT8188
- Add basic platform setup.
- Add MT8188 documentation at docs/plat/.
- Add generic CPU helper functions.
- Add basic register address.
- Add mtk_pm.c in lib/pm
TEST=build pass
BUG=b:236331724
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I5f8617c42ffba2c9d3a16f3980cb75fda5624031
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| a59cbd9e | 05-Sep-2022 |
Bo-Chen Chen <rex-bc.chen@mediatek.com> |
refator(mediatek): remove unused files
We do not use oem_svc.[c|h], so remove them.
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I0afb64d997cf4e23063f4fa2226e8d2649d22574
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| 3374752f | 05-Sep-2022 |
Bo-Chen Chen <rex-bc.chen@mediatek.com> |
refator(mediatek): move drivers folder in common to plat/mediatek
We plan to put some soc related drivers in common/drivers. To reduce
confision, we move them to plat/mediatek.
Signed-off-by: Bo-Ch
refator(mediatek): move drivers folder in common to plat/mediatek
We plan to put some soc related drivers in common/drivers. To reduce
confision, we move them to plat/mediatek.
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I6b344e660f40a23b15151aab073d3045b28f52aa
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| 4a81e91f | 20-Jun-2022 |
Himanshu Sharma <Himanshu.Sharma@arm.com> |
fix(n1sdp): mapping Run-time UART to IOFPGA UART0
Currently the Run-time UART is mapped to AP UART1 which is internally
routed to MCP UART1, so unsharing it from AP UART1 and mapping it to
IOFPGA UA
fix(n1sdp): mapping Run-time UART to IOFPGA UART0
Currently the Run-time UART is mapped to AP UART1 which is internally
routed to MCP UART1, so unsharing it from AP UART1 and mapping it to
IOFPGA UART0 for exclusiveness among the usage of the UARTs.
Signed-off-by: Himanshu Sharma <Himanshu.Sharma@arm.com>
Change-Id: I366740a971a880decf0d373e9055e7ebda5df53a
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| c58b9a8e | 23-Aug-2022 |
Rupinderjit Singh <rupinderjit.singh@arm.com> |
refactor(cpu): update IP names of Makalu CPU lib
* ASM files are renamed to have public IP names in their filename.
* updated other files to include ASM filename changes.
Signed-off-by: Rupin
refactor(cpu): update IP names of Makalu CPU lib
* ASM files are renamed to have public IP names in their filename.
* updated other files to include ASM filename changes.
Signed-off-by: Rupinderjit Singh <rupinderjit.singh@arm.com>
Change-Id: Ie899c512b11fd7c4312e3a808bb6b9d2376cdb8c
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| ef988aed | 09-Aug-2022 |
Rex-BC Chen <rex-bc.chen@mediatek.com> |
feat(mediatek): support coreboot BL31 loading
The ChromeOS project uses Coreboot as BL2 instead of MediaTek regular
bootloader, so we use COREBOOT flag to support Coreboot boot flow.
Signed-off-by:
feat(mediatek): support coreboot BL31 loading
The ChromeOS project uses Coreboot as BL2 instead of MediaTek regular
bootloader, so we use COREBOOT flag to support Coreboot boot flow.
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I45e95ea51e90158187452eba52fc58090d1c60a4
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| e2fe267d | 29-Aug-2022 |
Jorge Troncoso <jatron@google.com> |
chore: use tabs for indentation
This patch changes definitions of bl2_mem_params_descs to follow the
TF-A coding style documented at
https://trustedfirmware-a.readthedocs.io/en/latest/process/coding
chore: use tabs for indentation
This patch changes definitions of bl2_mem_params_descs to follow the
TF-A coding style documented at
https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-style.html
Signed-off-by: Jorge Troncoso <jatron@google.com>
Change-Id: I7bd99a50a79499aca0d349e49a3e095e6c5d2f08
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| 4a566b26 | 22-Aug-2022 |
Hari Nagalla <hnagalla@ti.com> |
feat(ti-k3): add support for J784S4 SoCs
The J784S4 SoC has two quad Cortex-A72 core clusters. This is the first
SoC in the K3 family with Quad cores in a A-72 cluster. So, a new board
configuration
feat(ti-k3): add support for J784S4 SoCs
The J784S4 SoC has two quad Cortex-A72 core clusters. This is the first
SoC in the K3 family with Quad cores in a A-72 cluster. So, a new board
configuration is introduced to support quad core clusters on the J784S4
SoC of the K3 family of devices.
See J784S4 Technical Reference Manual (SPRUJ52 - JUNE 2022)
for further details: http://www.ti.com/lit/zip/spruj52
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Change-Id: I0ed1f14ab32a56ae06e3df3161ace4597d14a48d
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| 394b9208 | 26-Jun-2022 |
Leon Chen <leon.chen@mediatek.com> |
feat(mediatek): implement generic platform port
Implement mandatory platform port functions. Receive
boot arguments from bl2, populate bl33 and bl32 image
entry structs, call each MTK initcall level
feat(mediatek): implement generic platform port
Implement mandatory platform port functions. Receive
boot arguments from bl2, populate bl33 and bl32 image
entry structs, call each MTK initcall levels
in these mandatory platform port functions.
After bl31_main exit and handover to 2nd boot loader,
mtk bl33 issues SMC and traps to TF-A to execute boot_to_kernel
and then handover to Linux kernel.
Signed-off-by: Leon Chen <leon.chen@mediatek.com>
Change-Id: I8d5a3511668fc749c4c71edf1ac700002cb5a9c8
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| 6a7e8ebf | 08-Jun-2022 |
Leon Chen <leon.chen@mediatek.com> |
refactor(mediatek): smc registration services
To modularize SMC handler, provide macro function in mtk_sip_svc.h.
Drivers register SMC name with value in mtk_sip_def.h, and bind the SMC
handler with
refactor(mediatek): smc registration services
To modularize SMC handler, provide macro function in mtk_sip_svc.h.
Drivers register SMC name with value in mtk_sip_def.h, and bind the SMC
handler with the SMC ID by calling DECLARE_SMC_HANDLER macro.
MTK_SIP_SMC_FROM_BL33_TABLE expand the SMC table as switch-case table
statically. DECLARE_SMC_HANDLER wrap SMC handlers with a structure and
put in a section.
During cold boot initialization, in MTK_EARLY_PLAT_INIT level parse the
section to assign each handler with an index. Each SMC request can be
identified with switch-case and take the index to call into
corresponding SMC handler.
Signed-off-by: Leon Chen <leon.chen@mediatek.com>
Change-Id: I03da212c786de0ec0ea646ba906065ecfcd82571
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| 52035dee | 20-Jun-2022 |
Leon Chen <leon.chen@mediatek.com> |
feat(mediatek): introduce mtk init framework
Provide six initcall levels for drivers/modules initialize HW
controllers or runtime arguments during cold boot.
The initcall level cold boot execution
feat(mediatek): introduce mtk init framework
Provide six initcall levels for drivers/modules initialize HW
controllers or runtime arguments during cold boot.
The initcall level cold boot execution order:
-MTK_EARLY_PLAT_INIT
Call before MMU enabled.
-MTK_ARCH_INIT
MMU Enabled, arch related init(GiC init, interrupt type registration).
-MTK_PLAT_SETUP_0_INIT
MTK driver init level 0.
-MTK_PLAT_SETUP_1_INIT
MTK driver init level 1.
-MTK_PLAT_RUNTIME_INIT
MTK driver init. After this initcall, TF-A handovers to MTK 2nd
bootloader.
-MTK_PLAT_BL33_DEFER_INIT
MTK 2nd bootloader traps to TF-A before handover to rich OS.
This initcall executed in the trap handler(boot_to_kernel).
Signed-off-by: Leon Chen <leon.chen@mediatek.com>
Change-Id: Icd7fe95372441db73c975ccb6ce77a6c529df1cc
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| 2f3f5939 | 29-May-2022 |
Leon Chen <leon.chen@mediatek.com> |
refactor(mediatek): partition MTK SiP SMC ID
Manage MTK SiP SMC ID with macros for 32/64 bit and
function declaration code generation.
Partition SMC ID with different exception level sources.
Signe
refactor(mediatek): partition MTK SiP SMC ID
Manage MTK SiP SMC ID with macros for 32/64 bit and
function declaration code generation.
Partition SMC ID with different exception level sources.
Signed-off-by: Leon Chen <leon.chen@mediatek.com>
Change-Id: I8966cd94f0d825e7ebae08833d2bd9fceedfd45e
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| 99d30b72 | 20-May-2022 |
Leon Chen <leon.chen@mediatek.com> |
feat(mediatek): extend SiP vendor subscription events
Leverage pubsub event framework to customize vendor's
event for better software modularization instead of adding
call entries in abstraction lay
feat(mediatek): extend SiP vendor subscription events
Leverage pubsub event framework to customize vendor's
event for better software modularization instead of adding
call entries in abstraction layer for customized platform function
with wrap-up define.
Signed-off-by: Leon Chen <leon.chen@mediatek.com>
Change-Id: I48be2303c45f759776fa2baa1c21130c1a8f0fa3
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| e0bbc190 | 13-Jan-2021 |
Lionel Debieve <lionel.debieve@st.com> |
feat(stm32mp1): allow to override MTD base offset
Add an external parameter STM32MP_FORCE_MTD_START_OFFSET that allows to
override the default FIP offset used to read the first programmed image.
It
feat(stm32mp1): allow to override MTD base offset
Add an external parameter STM32MP_FORCE_MTD_START_OFFSET that allows to
override the default FIP offset used to read the first programmed image.
It can be used for NOR, RAW_NAND or SPI_NAND boot device.
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: Ibe664aae0e5ee90dd6629e544c9e034d751fffed
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| d3434dca | 18-Aug-2021 |
Yann Gautier <yann.gautier@foss.st.com> |
feat(stm32mp1): manage second NAND OTP on STM32MP13
On STM32MP13, 2 OTP fuses can be used to configure NAND devices.
By default OTP CFG9 is used for sNAND. A new OTP (CFG10) is used
to configure raw
feat(stm32mp1): manage second NAND OTP on STM32MP13
On STM32MP13, 2 OTP fuses can be used to configure NAND devices.
By default OTP CFG9 is used for sNAND. A new OTP (CFG10) is used
to configure raw NAND. Thanks to bit 0 of CFG10 OTP, this default
configuration can be switched.
For sNAND on STM32MP13, the NAND_PARAM_STORED_IN_OTP is not used.
The sNAND parameters have to be taken from OTP bits.
Change-Id: Ib95e0f9b9e66179a58b07f723ea01dce68b96475
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
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| 9ee2510b | 13-Apr-2021 |
Lionel Debieve <lionel.debieve@foss.st.com> |
feat(stm32mp1): add define for external scratch buffer for nand devices
Override the default platform function to use an external buffer
on STM32MP13 platform.
It allows to use a temporary buffer lo
feat(stm32mp1): add define for external scratch buffer for nand devices
Override the default platform function to use an external buffer
on STM32MP13 platform.
It allows to use a temporary buffer located at the SRAM1 memory end.
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Change-Id: Ibd84bb336c60af24608268916b3a18bb5a0fa3db
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| 0c0bab0c | 25-Aug-2022 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge changes from topic "ffa_el3_spmc" into integration
* changes:
feat(tsp): enable test cases for EL3 SPMC
feat(tsp): increase stack size for tsp
feat(tsp): add ffa_helpers to enable more F
Merge changes from topic "ffa_el3_spmc" into integration
* changes:
feat(tsp): enable test cases for EL3 SPMC
feat(tsp): increase stack size for tsp
feat(tsp): add ffa_helpers to enable more FF-A functionality
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| 5b7bd2af | 09-Aug-2022 |
Shruti Gupta <shruti.gupta@arm.com> |
feat(tsp): increase stack size for tsp
TSP testcases for EL3 SPMC have higher stack usage.
Change-Id: Ib5bfdccc6d0f65174e257f3b0e8b41bcd3c704a6
Signed-off-by: Shruti Gupta <shruti.gupta@arm.com> |
| 19037a71 | 24-Aug-2022 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge changes from topic "ffa_el3_spmc" into integration
* changes:
feat(tsp): add FF-A support to the TSP
feat(fvp/tsp_manifest): add example manifest for TSP
fix(spmc): fix relinquish valida
Merge changes from topic "ffa_el3_spmc" into integration
* changes:
feat(tsp): add FF-A support to the TSP
feat(fvp/tsp_manifest): add example manifest for TSP
fix(spmc): fix relinquish validation check
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| 51efe883 | 24-Aug-2022 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge "feat(qemu): increase size of bl31" into integration |
| 4264bd33 | 23-Aug-2022 |
Akshay Belsare <Akshay.Belsare@amd.com> |
fix(zynqmp): fix for incorrect afi write mask value
Currently, the AFIFM6_WRCTRL bus-width configuration is not happening
correctly due to the wrong register write mask value. To fix this issue
upda
fix(zynqmp): fix for incorrect afi write mask value
Currently, the AFIFM6_WRCTRL bus-width configuration is not happening
correctly due to the wrong register write mask value. To fix this issue
updated the mask value handling logic.
Signed-off-by: Nava kishore Manne <nava.kishore.manne@amd.com>
Signed-off-by: Akshay Belsare <Akshay.Belsare@amd.com>
Acked-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Change-Id: I8443c369a84339018310cfb6cd498d21474da3e4
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| 3cf080ed | 23-Nov-2021 |
Marc Bonnici <marc.bonnici@arm.com> |
feat(fvp/tsp_manifest): add example manifest for TSP
Add an example manifest for the EL3 SPMC on the FVP Platform
that allows booting the TSP example partition.
Signed-off-by: Marc Bonnici <marc.bo
feat(fvp/tsp_manifest): add example manifest for TSP
Add an example manifest for the EL3 SPMC on the FVP Platform
that allows booting the TSP example partition.
Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: Ie7f40328e0313abb5b1a121dfdc22a5f7387587f
Signed-off-by: Shruti Gupta <shruti.gupta@arm.com>
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| a3f97f66 | 09-May-2022 |
Yann Gautier <yann.gautier@foss.st.com> |
feat(stm32mp1): manage STM32MP13 rev.Y
The new SoC version for STM32MP13 is the revision Y. The register
SYSCFG_IDC is updated for this new version with the value 0x1003.
The function stm32mp_get_so
feat(stm32mp1): manage STM32MP13 rev.Y
The new SoC version for STM32MP13 is the revision Y. The register
SYSCFG_IDC is updated for this new version with the value 0x1003.
The function stm32mp_get_soc_name() should also be updated to manage
this new SoC revision.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I4f2fa5f1503f17db93d8413c79c2b7a18d279f9b
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| 53d5b8ff | 14-Aug-2019 |
Yann Gautier <yann.gautier@st.com> |
feat(st): enable MMC_FLAG_SD_CMD6 for SD-cards
This flag allows switching to High-Speed mode on SD-cards.
The gain is ~44ms when using SP_min, and ~55ms with OP-TEE.
Change-Id: Ic396c6a14201580b5e5
feat(st): enable MMC_FLAG_SD_CMD6 for SD-cards
This flag allows switching to High-Speed mode on SD-cards.
The gain is ~44ms when using SP_min, and ~55ms with OP-TEE.
Change-Id: Ic396c6a14201580b5e5627e6174b85b437b87cae
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| 0e6977ee | 19-Jan-2022 |
Jens Wiklander <jens.wiklander@linaro.org> |
feat(qemu): increase size of bl31
Increases the SRAM to a full 1MB and also increase BL31 size to have
room to spare for debugging.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Change-
feat(qemu): increase size of bl31
Increases the SRAM to a full 1MB and also increase BL31 size to have
room to spare for debugging.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Change-Id: I584f9d409a1f653a3dfc7cf2b95706ada367c70e
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