| 92eba866 | 07-Jul-2022 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "fix(morello): move BL31 to run from DRAM space" into integration |
| c8d6e581 | 07-Jul-2022 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge changes from topic "sgi-updates-jul-2022" into integration
* changes:
feat(sgi): bump bl1 rw size
refactor(sgi): rewrite address space size definitions |
| 94df8da3 | 25-Jan-2022 |
Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com> |
feat(sgi): bump bl1 rw size
Increase BL1 RW size by 16 KiB to accommodate for future development.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: I21626a97de
feat(sgi): bump bl1 rw size
Increase BL1 RW size by 16 KiB to accommodate for future development.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: I21626a97de4a6c98c25b93b9f79e16325c6e4349
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| 1d74b4bb | 25-Jan-2022 |
Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com> |
refactor(sgi): rewrite address space size definitions
The value of the macro CSS_SGI_REMOTE_CHIP_MEM_OFFSET can be different
across all the Neoverse reference design platforms. This value depends
on
refactor(sgi): rewrite address space size definitions
The value of the macro CSS_SGI_REMOTE_CHIP_MEM_OFFSET can be different
across all the Neoverse reference design platforms. This value depends
on the number of address bits used per chip. So let all platforms define
CSS_SGI_ADDR_BITS_PER_CHIP which specifies the number of address bits
used per chip.
In addition to this, reuse the definition of CSS_SGI_ADDR_BITS_PER_CHIP
for single chip platforms and CSS_SGI_REMOTE_CHIP_MEM_OFFSET for multi-
chip platforms to determine the maximum address space size. Also,
increase the RD-N2 multi-chip address space per chip from 4TB to 64TB.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: If5e69ec26c2389304c71911729d4addbdf8b2686
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| 05330a49 | 23-Jun-2022 |
Manoj Kumar <manoj.kumar3@arm.com> |
fix(morello): move BL31 to run from DRAM space
The EL3 runtime firmware has been running from internal trusted
SRAM space on the Morello platform. Due to unavailability of tag
support for the intern
fix(morello): move BL31 to run from DRAM space
The EL3 runtime firmware has been running from internal trusted
SRAM space on the Morello platform. Due to unavailability of tag
support for the internal trusted SRAM this becomes a problem if
we enable capability pointers in BL31.
To support capability pointers in BL31 it has to be run from the
main DDR memory space. This patch updates the Morello platform
configuration such that BL31 is loaded and run from DDR space.
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
Change-Id: I16d4d757fb6f58c364f5133236d50fc06845e0b4
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| bfd7c881 | 04-Jul-2022 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
feat(zynqmp): resolve the misra 10.1 warnings
MISRA Violation: MISRA-C:2012 R.10.1
1) The expression of non-boolean essential type is being interpreted as a
boolean value for the operator.
2) The op
feat(zynqmp): resolve the misra 10.1 warnings
MISRA Violation: MISRA-C:2012 R.10.1
1) The expression of non-boolean essential type is being interpreted as a
boolean value for the operator.
2) The operand to the operator does not have an essentially unsigned type.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I97bbc056f4fee167742429e144144ba793bf77b3
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| de1ab9fe | 05-Jul-2022 |
Yann Gautier <yann.gautier@foss.st.com> |
fix(stm32mp13): correct USART addresses
On STM32MP13, USART1 and USART2 addresses are 0x4C000000 and 0x4C001000.
Whereas on STM32MP15, the addresses were 0x5C000000 and 0x4000E000.
Use dedicated fla
fix(stm32mp13): correct USART addresses
On STM32MP13, USART1 and USART2 addresses are 0x4C000000 and 0x4C001000.
Whereas on STM32MP15, the addresses were 0x5C000000 and 0x4000E000.
Use dedicated flags to choose the correct address, that could be use
for early or crash console.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I98bd97a0ac8b0408a50376801e2a1961b241a3d6
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| 10f6dc78 | 13-Apr-2021 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
feat(stm32mp13): change BL33 memory mapping
U-Boot is loaded at the beginning of the DDR:
STM32MP_DDR_BASE = 0xC0000000.
This patch remove the need to use the 0x100000 offset, reserved
on STM32MP15
feat(stm32mp13): change BL33 memory mapping
U-Boot is loaded at the beginning of the DDR:
STM32MP_DDR_BASE = 0xC0000000.
This patch remove the need to use the 0x100000 offset, reserved
on STM32MP15 for flashlayout.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I8d0a93f4db411cf59838e635a315c729cccee269
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| 1dab28f9 | 24-Feb-2022 |
Lionel Debieve <lionel.debieve@foss.st.com> |
feat(stm32mp1): retrieve FIP partition by type UUID
Modify the function to retrieve the FIP partition looking
the UUID type define for FIP. If not defined, compatibility
used to find the FIP partiti
feat(stm32mp1): retrieve FIP partition by type UUID
Modify the function to retrieve the FIP partition looking
the UUID type define for FIP. If not defined, compatibility
used to find the FIP partition by name.
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Change-Id: I76634dea891f51d913a549fb9a077cf7284d5cb2
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| 8fc6fb5c | 30-Jun-2022 |
Yann Gautier <yann.gautier@st.com> |
refactor(stm32mp1): update PLAT_PARTITION_MAX_ENTRIES
Fix the maximum partition number to a default value. It must
also take care of the extra partition when FWU feature is enabled.
Change-Id: Ib64
refactor(stm32mp1): update PLAT_PARTITION_MAX_ENTRIES
Fix the maximum partition number to a default value. It must
also take care of the extra partition when FWU feature is enabled.
Change-Id: Ib64b1f19f1f0514f7e89d35fc367facd6df54bed
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| 717daadc | 05-Jul-2022 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "jas/rmm-el3-ifc" into integration
* changes:
docs(rmmd): document EL3-RMM Interfaces
feat(rmmd): add support to create a boot manifest
fix(rme): use RMM shared buffer
Merge changes from topic "jas/rmm-el3-ifc" into integration
* changes:
docs(rmmd): document EL3-RMM Interfaces
feat(rmmd): add support to create a boot manifest
fix(rme): use RMM shared buffer for attest SMCs
feat(rmmd): add support for RMM Boot interface
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| 1ae014dd | 05-Jul-2022 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "feat(arm): forbid running RME-enlightened BL31 from DRAM" into integration |
| 1d0ca40e | 25-Apr-2022 |
Javier Almansa Sobrino <javier.almansasobrino@arm.com> |
feat(rmmd): add support to create a boot manifest
This patch also adds an initial RMM Boot Manifest (v0.1) for fvp
platform.
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Ch
feat(rmmd): add support to create a boot manifest
This patch also adds an initial RMM Boot Manifest (v0.1) for fvp
platform.
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I1374f8f9cb207028f1820953cd2a5cf6d6c3b948
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| dc65ae46 | 13-Apr-2022 |
Javier Almansa Sobrino <javier.almansasobrino@arm.com> |
fix(rme): use RMM shared buffer for attest SMCs
Use the RMM shared buffer to attestation token and signing key SMCs.
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id:
fix(rme): use RMM shared buffer for attest SMCs
Use the RMM shared buffer to attestation token and signing key SMCs.
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I313838b26d3d9334fb0fe8cd4b229a326440d2f4
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| 8c980a4a | 24-Nov-2021 |
Javier Almansa Sobrino <javier.almansasobrino@arm.com> |
feat(rmmd): add support for RMM Boot interface
This patch adds the infrastructure needed to pass boot arguments from
EL3 to RMM and allocates a shared buffer between both worlds that can
be used, am
feat(rmmd): add support for RMM Boot interface
This patch adds the infrastructure needed to pass boot arguments from
EL3 to RMM and allocates a shared buffer between both worlds that can
be used, among others, to pass a boot manifest to RMM. The buffer is
composed a single memory page be used by a later EL3 <-> RMM interface
by all CPUs.
The RMM boot manifest is not implemented by this patch.
In addition to that, this patch also enables support for RMM when
RESET_TO_BL31 is enabled.
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I855cd4758ee3843eadd9fb482d70a6d18954d82a
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| 1164a59c | 04-Jul-2022 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
feat(arm): forbid running RME-enlightened BL31 from DRAM
According to Arm CCA security model [1],
"Root world firmware, including Monitor, is the most trusted CCA
component on application PE. It en
feat(arm): forbid running RME-enlightened BL31 from DRAM
According to Arm CCA security model [1],
"Root world firmware, including Monitor, is the most trusted CCA
component on application PE. It enforces CCA security guarantees for
not just Realm world, but also for Secure world and for itself.
It is expected to be small enough to feasibly fit in on-chip memory,
and typically needs to be available early in the boot process when
only on-chip memory is available."
For these reasons, it is expected that "monitor code executes entirely
from on-chip memory."
This precludes usage of ARM_BL31_IN_DRAM for RME-enlightened firmware.
[1] Arm DEN0096 A.a, section 7.3 "Use of external memory by CCA".
Change-Id: I752eb45f1e6ffddc7a6f53aadcc92a3e71c1759f
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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| 2d8e80c2 | 30-Jun-2022 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes from topics "binary-format-sp", "od/meas-boot-spmc" into integration
* changes:
feat(spm): add tpm event log node to spmc manifest
fix(measured-boot): add SP entries to event_log_m
Merge changes from topics "binary-format-sp", "od/meas-boot-spmc" into integration
* changes:
feat(spm): add tpm event log node to spmc manifest
fix(measured-boot): add SP entries to event_log_metadata
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| 722ca35e | 30-Jun-2022 |
Yann Gautier <yann.gautier@st.com> |
feat(stm32mp15): manage OP-TEE shared memory
On STM32MP15, there is currently an OP-TEE shared memory area at the end
of the DDR. But this area will in term be removed. To allow a smooth
transition,
feat(stm32mp15): manage OP-TEE shared memory
On STM32MP15, there is currently an OP-TEE shared memory area at the end
of the DDR. But this area will in term be removed. To allow a smooth
transition, a new flag is added (STM32MP15_OPTEE_RSV_SHM). It reflects
the OP-TEE flag: CFG_CORE_RESERVED_SHM. The flag is enabled by default
(no behavior change). It will be set to 0 when OP-TEE is aligned, and
then later be removed.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I91146cd8a26a24be22143c212362294c1e880264
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| 57ab7497 | 29-Jun-2022 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes from topic "xlnx_zynqmp_misra_fix1" into integration
* changes:
fix(zynqmp): resolve the misra 8.6 warnings
fix(zynqmp): resolve the misra 4.6 warnings |
| caca0e57 | 28-Jun-2022 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "feat(stm32mp1): save boot auth status and partition info" into integration |
| 4bbdc391 | 28-Jun-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "HEAD" into integration
* changes:
feat(synquacer): add FWU Multi Bank Update support
feat(synquacer): add TBBR support
feat(synquacer): add BL2 support
refactor(syn
Merge changes from topic "HEAD" into integration
* changes:
feat(synquacer): add FWU Multi Bank Update support
feat(synquacer): add TBBR support
feat(synquacer): add BL2 support
refactor(synquacer): move common source files
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| a1938252 | 23-May-2022 |
Jassi Brar <jaswinder.singh@linaro.org> |
feat(synquacer): add FWU Multi Bank Update support
Add FWU Multi Bank Update support. This reads the platform metadata
and update the FIP base address so that BL2 can load correct BL3X
based on the
feat(synquacer): add FWU Multi Bank Update support
Add FWU Multi Bank Update support. This reads the platform metadata
and update the FIP base address so that BL2 can load correct BL3X
based on the boot index.
Cc: Sumit Garg <sumit.garg@linaro.org>
Cc: Masahisa Kojima <masahisa.kojima@linaro.org>
Cc: Manish V Badarkhe <manish.badarkhe@arm.com>
Cc: Leonardo Sandoval <leonardo.sandoval@linaro.org>
Change-Id: I5d96972bc4b3b9a12a8157117e53a05da5ce89f6
Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
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| 19aaeea0 | 03-Mar-2022 |
Jassi Brar <jaswinder.singh@linaro.org> |
feat(synquacer): add TBBR support
enable Trusted-Boot for Synquacer platform.
Cc: Sumit Garg <sumit.garg@linaro.org>
Cc: Masahisa Kojima <masahisa.kojima@linaro.org>
Cc: Manish V Badarkhe <manish.b
feat(synquacer): add TBBR support
enable Trusted-Boot for Synquacer platform.
Cc: Sumit Garg <sumit.garg@linaro.org>
Cc: Masahisa Kojima <masahisa.kojima@linaro.org>
Cc: Manish V Badarkhe <manish.badarkhe@arm.com>
Cc: Leonardo Sandoval <leonardo.sandoval@linaro.org>
Change-Id: I2608b4d573d95d55da1fc5544333e0dbf3f763f2
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
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| 48ab3904 | 03-Mar-2022 |
Jassi Brar <jaswinder.singh@linaro.org> |
feat(synquacer): add BL2 support
Add BL2 support by default. Move the legacy mode behind the
RESET_TO_BL31 define.
Cc: Sumit Garg <sumit.garg@linaro.org>
Cc: Masahisa Kojima <masahisa.kojima@linaro
feat(synquacer): add BL2 support
Add BL2 support by default. Move the legacy mode behind the
RESET_TO_BL31 define.
Cc: Sumit Garg <sumit.garg@linaro.org>
Cc: Masahisa Kojima <masahisa.kojima@linaro.org>
Cc: Manish V Badarkhe <manish.badarkhe@arm.com>
Cc: Leonardo Sandoval <leonardo.sandoval@linaro.org>
Change-Id: Ic490745a7e8f6114172733428ebd6bd6adfcc1ec
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
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| 3ba82d5f | 03-Mar-2022 |
Jassi Brar <jaswinder.singh@linaro.org> |
refactor(synquacer): move common source files
Prepare for introduction of BL2 support by moving
reusable files from BL31_SOURCES into PLAT_BL_COMMON_SOURCES
Cc: Sumit Garg <sumit.garg@linaro.org>
C
refactor(synquacer): move common source files
Prepare for introduction of BL2 support by moving
reusable files from BL31_SOURCES into PLAT_BL_COMMON_SOURCES
Cc: Sumit Garg <sumit.garg@linaro.org>
Cc: Masahisa Kojima <masahisa.kojima@linaro.org>
Cc: Manish V Badarkhe <manish.badarkhe@arm.com>
Cc: Leonardo Sandoval <leonardo.sandoval@linaro.org>
Change-Id: I21137cdd40d027cfa77f1dec3598ee85d4873581
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
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