fix(zynqmp): resolve the misra 4.6 warnings

MISRA Violation: MISRA-C:2012 R.4.6
- Using basic numerical type int rather than a typedef
that includes size and signedness information.

Change-Id: Id85

fix(zynqmp): resolve the misra 4.6 warnings

MISRA Violation: MISRA-C:2012 R.4.6
- Using basic numerical type int rather than a typedef
that includes size and signedness information.

Change-Id: Id85e69b29b124052b4a87462ce27fcdfc00c13c9
Signed-off-by: HariBabu Gattem <haribabu.gattem@amd.com>

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Merge "feat(versal): update macro name to generic and move to common place" into integration

Merge changes from topic "provencore-spd" into integration

* changes:
feat(zynqmp): add support for ProvenCore
feat(services): add a SPD for ProvenCore
feat(gic): add APIs to raise NS and S-EL

Merge changes from topic "provencore-spd" into integration

* changes:
feat(zynqmp): add support for ProvenCore
feat(services): add a SPD for ProvenCore
feat(gic): add APIs to raise NS and S-EL1 SGIs

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feat(zynqmp): add support for ProvenCore

ProvenCore requires secure SGIs to be handled at S-EL1. This patch
overrides the default ZynqMP configuration to handle them at EL3 in case
ProvenCore SPD is

feat(zynqmp): add support for ProvenCore

ProvenCore requires secure SGIs to be handled at S-EL1. This patch
overrides the default ZynqMP configuration to handle them at EL3 in case
ProvenCore SPD is enabled.

Signed-off-by: Jeremie Corbier <jeremie.corbier@provenrun.com>
Signed-off-by: Mélanie Favre <melanie.favre@provenrun.com>
Change-Id: I2e36d2983f82fbb9b7acf7e18791b8ed92811b60

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fix(intel): fix asynchronous read response by copying data to input buffer

To fix that response should not be NULL when there is response data
need to be sent to input buffer by SDM.

Signed-off-by:

fix(intel): fix asynchronous read response by copying data to input buffer

To fix that response should not be NULL when there is response data
need to be sent to input buffer by SDM.

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Id70289521792f5f995456d2e67e18f0185ca3fc0

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fix(intel): fix Mac verify update and finalize for return response data

To fix that the response data is returned when the source size ready
is still fit for response data size.

Signed-off-by: Sieu

fix(intel): fix Mac verify update and finalize for return response data

To fix that the response data is returned when the source size ready
is still fit for response data size.

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Id8924137a5c33888e7042e9ab0e0e8c49b4a41ed

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feat(sgi): enable css implementation of warm reset

Enable the CSS implementation of the warm reset for the rdn2 platform.

In addition to these changes, fix coding style issues that are not
directl

feat(sgi): enable css implementation of warm reset

Enable the CSS implementation of the warm reset for the rdn2 platform.

In addition to these changes, fix coding style issues that are not
directly related to the code being introduced in this patch.

Change-Id: I75128d8bbcccbc26cf1e904691c7ef71349c622f
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>

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feat(scmi): send powerdown request to online secondary cpus

To initiate a reset or reboot, the nonsecure OS invokes the PSCI
SYSTEM_RESET function from any one core. As per the PSCI specification,
i

feat(scmi): send powerdown request to online secondary cpus

To initiate a reset or reboot, the nonsecure OS invokes the PSCI
SYSTEM_RESET function from any one core. As per the PSCI specification,
it is the responsibility of firmware to implement the system view of
the reset or reboot operation. For the platforms supported by CSS,
trigger the reset/reboot operation by sending an SGI to rest all CPUs
which are online. The CPUs respond to this interrupt by initiating its
powerdown sequence.

In addition to these changes, fix coding style issues that are not
directly related to the code being introduced in this patch.

Change-Id: I547253ee28ef7eefa78180d016893671a406bbfa
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>

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feat(plat/arm/css): add interrupt handler for reboot request

Add platform specific interrupt handler for handling the reboot of
all CPU's. On shutdown/reboot, only one CPU invoke PSCI and enter into

feat(plat/arm/css): add interrupt handler for reboot request

Add platform specific interrupt handler for handling the reboot of
all CPU's. On shutdown/reboot, only one CPU invoke PSCI and enter into
trusted firmware. The CPU which entered trusted firmware signals the
rest of the cores which are online using SGI to initiate power down
sequence. On receiving the SGI, the handler will power down the
GIC redistributor interface of the respective core, configure the power
control register and power down the CPU by executing wfi.

In addition to these changes, fix coding style issues that are not
directly related to the code being introduced in this patch.

Change-Id: I4917dfdc47be5ce7367bee629486a6344cdd706f
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>

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feat(plat/arm/css): add per-cpu power down support for warm reset

Add a new function to setup a SGI interrupt that will be used to trigger
a request for per-cpu power down when executing the PSCI SY

feat(plat/arm/css): add per-cpu power down support for warm reset

Add a new function to setup a SGI interrupt that will be used to trigger
a request for per-cpu power down when executing the PSCI SYSTEM_RESET
request. This will be used on CSS platform that require all the CPUs to
execute the CPU specific power down sequence to complete a warm reboot
sequence in which only the CPUs are power cycled.

Change-Id: I80da0f6c3cd0c5c442c82239ba1e1f773821a7f5
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>

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Merge "fix(versal): route GIC IPI interrupts during setup" into integration

Merge "fix(zynqmp): move debug bl31 based address back to OCM" into integration

fix(versal): route GIC IPI interrupts during setup

If primary core is down, then IPI interrupt should be
routed to another core for processing.

Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
Chan

fix(versal): route GIC IPI interrupts during setup

If primary core is down, then IPI interrupt should be
routed to another core for processing.

Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
Change-Id: I01d7c4232a18c0c3b3f3f9ddadfa6ff5bd2f2471

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feat(gic): add APIs to raise NS and S-EL1 SGIs

This patch adds two helper functions:
- plat_ic_raise_ns_sgi to raise a NS SGI
- plat_ic_raise_s_el1_sgi to raise a S-EL1 SGI

Signed-off-by: Florian

feat(gic): add APIs to raise NS and S-EL1 SGIs

This patch adds two helper functions:
- plat_ic_raise_ns_sgi to raise a NS SGI
- plat_ic_raise_s_el1_sgi to raise a S-EL1 SGI

Signed-off-by: Florian Lugou <florian.lugou@provenrun.com>
Change-Id: I6f262dd1da1d77fec3f850eb74189e726b8e24da

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Merge changes from topic "xilinx-pm-misc-changes" into integration

* changes:
fix(xilinx): update define for ZynqMP specific functions
fix(xilinx): remove unnecessary header include
fix(xilinx

Merge changes from topic "xilinx-pm-misc-changes" into integration

* changes:
fix(xilinx): update define for ZynqMP specific functions
fix(xilinx): remove unnecessary header include
fix(xilinx): include missing header

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Merge changes from topic "xilinx-misc-changes" into integration

* changes:
chore(zynqmp): fix comment style in zynqmp_def.h
chore(versal): add missing dot at the end of sentence
fix(zynqmp): r

Merge changes from topic "xilinx-misc-changes" into integration

* changes:
chore(zynqmp): fix comment style in zynqmp_def.h
chore(versal): add missing dot at the end of sentence
fix(zynqmp): remove additional 0x in %p print
fix(versal): fix Misra-C violations in bl31_setup and pm_svc_main

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fix(xilinx): update define for ZynqMP specific functions

Instead of exclude code for Versal, define only for ZynqMP.
For new platforms this code should be excluded so instead of
excluding for all pl

fix(xilinx): update define for ZynqMP specific functions

Instead of exclude code for Versal, define only for ZynqMP.
For new platforms this code should be excluded so instead of
excluding for all platform, define only for ZynqMP.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I45798dadc0f374c5794f517f7d0158675a75caa9

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fix(xilinx): remove unnecessary header include

Platform specific IPI header inclusion is not required
in common IPI source file. So remove inclusion of the same.

Signed-off-by: Rajan Vaja <rajan.va

fix(xilinx): remove unnecessary header include

Platform specific IPI header inclusion is not required
in common IPI source file. So remove inclusion of the same.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I6686757f00370c6ec42b5ee2c44ea5cd13da70c0

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fix(xilinx): include missing header

pm_ipi.h needs some definitions from stddef.h so include it.
Currently it is working because required file is included
indirectly due to other includes.

Signed-o

fix(xilinx): include missing header

pm_ipi.h needs some definitions from stddef.h so include it.
Currently it is working because required file is included
indirectly due to other includes.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: Ic4a6c469c3152e21eaeb365ba96f3a29f14593bf

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chore(zynqmp): fix comment style in zynqmp_def.h

Add missing space in one line comment to follow common coding style.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: Idebf8f34bf48444e

chore(zynqmp): fix comment style in zynqmp_def.h

Add missing space in one line comment to follow common coding style.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: Idebf8f34bf48444ee20a68ac3e6fd7f5a41bf8b0

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chore(versal): add missing dot at the end of sentence

Add missing dot at the end of sentence.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I356e65fd8c572c12795e3492dd02d73f48cb4b67

fix(zynqmp): remove additional 0x in %p print

%p is already printing value in hex that's why 0x prefix is not needed.
Origin message looks like this
"NOTICE: Can't read DT at 0x0x100000"
and after

fix(zynqmp): remove additional 0x in %p print

%p is already printing value in hex that's why 0x prefix is not needed.
Origin message looks like this
"NOTICE: Can't read DT at 0x0x100000"
and after fixing
"NOTICE: Can't read DT at 0x100000"

Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: If83c485a61441f6105d8cbd797f04060dfce2817

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fix(versal): fix Misra-C violations in bl31_setup and pm_svc_main

Fix some Misra-C violations. The similar fixes were done by commit
eb0d2b17722c ("fix(zynqmp): resolve misra R15.6 warnings") and co

fix(versal): fix Misra-C violations in bl31_setup and pm_svc_main

Fix some Misra-C violations. The similar fixes were done by commit
eb0d2b17722c ("fix(zynqmp): resolve misra R15.6 warnings") and commit
dd1fe7178b57 ("fix(zynqmp): resolve misra R14.4 warnings").

Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I3ffa92724a09871f7f99c9ac6c326994c165e9bd

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fix(zynqmp): ensure memory write finish with dsb()

GICD reg write must complete before core goes to idle
mode. Achieve this with dsb() barrier instruction in IPI
ISR

Signed-off-by: Tanmay Shah <tan

fix(zynqmp): ensure memory write finish with dsb()

GICD reg write must complete before core goes to idle
mode. Achieve this with dsb() barrier instruction in IPI
ISR

Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
Change-Id: I5af42ca901567ee5e54a5434ebe3e673a92cb9be

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fix(zynqmp): move debug bl31 based address back to OCM

The commit 389594dfa7e6 ("fix(zynqmp): move bl31 with DEBUG=1 back to OCM")
tried to move address to OCM but address was actually out of OCM an

fix(zynqmp): move debug bl31 based address back to OCM

The commit 389594dfa7e6 ("fix(zynqmp): move bl31 with DEBUG=1 back to OCM")
tried to move address to OCM but address was actually out of OCM and likely
it was typo. Correct default address should be 0xfffe5000. If TF-A size is
bigger please select location DDR which should be fine for DEBUG cases.

Reported-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I055f3a59cdca527f6029fcc2a19d76be35924d24

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