feat(imx8mp): add hab and map required memory blocks

In order for HAB to perform operations, memory regions has to be mapped
in TF-A, which HAB ROM code would use internally.

Include those memory b

feat(imx8mp): add hab and map required memory blocks

In order for HAB to perform operations, memory regions has to be mapped
in TF-A, which HAB ROM code would use internally.

Include those memory blocks for i.MX8M+ SoC. Of a special note, the DRAM
block is mapped with complete size available on the platform and uses
MT_RW attributes, this is required to minimize the size of translation
tables and provide a possibility to exchange the execution results
between EL3 and EL1&2, see details in [1].

Link: [1]: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/16880
Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Change-Id: I986cdce434d1ec9ea8b3c0d5599edde55b9b30f8

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feat(imx8mn): add hab and map required memory blocks

In order for HAB to perform operations, memory regions has to be mapped
in TF-A, which HAB ROM code would use internally.

Include those memory b

feat(imx8mn): add hab and map required memory blocks

In order for HAB to perform operations, memory regions has to be mapped
in TF-A, which HAB ROM code would use internally.

Include those memory blocks for i.MX8MN SoC. Of a special note, the DRAM
block is mapped with complete size available on the platform and uses
MT_RW attributes, this is required to minimize the size of translation
tables and provide a possibility to exchange the execution results
between EL3 and EL1&2, see details in [1].

Link: [1]: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/16880
Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Change-Id: If7a2b718658db452871e1ae56b71a4983e8ef2fe

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feat(imx8mm): add hab and map required memory blocks

In order for HAB to perform operations, memory regions has to be mapped
in TF-A, which HAB ROM code would use internally.

Include those memory b

feat(imx8mm): add hab and map required memory blocks

In order for HAB to perform operations, memory regions has to be mapped
in TF-A, which HAB ROM code would use internally.

Include those memory blocks for i.MX8MM SoC. Of a special note, the DRAM
block is mapped with complete size available on the platform and uses
MT_RW attributes, this is required to minimize the size of translation
tables and provide a possibility to exchange the execution results
between EL3 and EL1&2, see details in [1].

Link: [1]: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/16880
Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Change-Id: I6a3a3d7105b85c2f4ab6ea6cfbca67c9a325eb11

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Merge "feat(fvp): build delegated attestation in BL31" into integration

feat(rdn2): enable extended SPI support

Enable the GIC_EXT_INTID configuration to support extended interrupt
IDs for RD-N2 multichip platform.

Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Cha

feat(rdn2): enable extended SPI support

Enable the GIC_EXT_INTID configuration to support extended interrupt
IDs for RD-N2 multichip platform.

Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Change-Id: Ic8d59ba0e692e5f13f3cdeffc64d76cd4741aa11

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feat(rdn2): add SPI ID ranges for RD-N2 multichip platform

Add the SPI ID ranges for various chips on RD-N2 multichip platform
(rdn2cfg2). Also fix the max SPI ID for chip#0 that was incorrectly
set

feat(rdn2): add SPI ID ranges for RD-N2 multichip platform

Add the SPI ID ranges for various chips on RD-N2 multichip platform
(rdn2cfg2). Also fix the max SPI ID for chip#0 that was incorrectly
set.
The SPI ranges for rdn2cfg2 platform are as shown below:
============================================
Chip# | CHIP_START_INTID | CHIP_END_INTID
============================================
0 | 32 | 511
1 | 512 | 991
2 | 4096 | 4575
3 | 4576 | 5055

Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Change-Id: I146944af1ffe52c300eef2ef48b1077a9559bf41

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Merge "chore(rpi3): remove redundant code" into integration

fix(versal_net): Enable a78 errata workarounds

TF-A is reporting that erratum are missing to be enabled.

Enable the Following errata workaround to Cortex-A78 AE CPU for versal_net
ERRATA_A78_AE_194

fix(versal_net): Enable a78 errata workarounds

TF-A is reporting that erratum are missing to be enabled.

Enable the Following errata workaround to Cortex-A78 AE CPU for versal_net
ERRATA_A78_AE_1941500
ERRATA_A78_AE_1951502
ERRATA_A78_AE_2376748
ERRATA_A78_AE_2395408

For further information refer to
https://developer.arm.com/documentation/SDEN1707912/1300/

Signed-off-by: Akshay Belsare <Akshay.Belsare@amd.com>
Change-Id: Ib7fc16e035feab1dfbd88c1f8ce128b057eee86d

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feat(fvp): build delegated attestation in BL31

Right now, the delegated attestation module is not used in TF-A. This
means it's not even getting built and so the CI system cannot detect
build regres

feat(fvp): build delegated attestation in BL31

Right now, the delegated attestation module is not used in TF-A. This
means it's not even getting built and so the CI system cannot detect
build regressions.

Eventually, delegated attestation will be involved in a new runtime
service exposed by BL31 to lower exception levels. We are not there
yet but let's already include it into BL31 image, so we get build
coverage and static analysis on the code. Note that we make sure to
cover both PLAT_RSS_NOT_SUPPORTED=0 and PLAT_RSS_NOT_SUPPORTED=1
configurations.

Delegated attestation is currently made dependent on measured boot
support. This dependency is not at the source code level (attestation
code does not invoke any measured boot interfaces) but it is rather a
logical dependency: attestation without boot measurements is not very
useful...

For now, this is good enough for our purpose but the conditions under
which the attestation code is included might change in the future.

Change-Id: I616715c3dd0418a1bbf1019df3ff9acd8461e705
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

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fix(versal): enable a72 erratum 859971 and 1319367

TF-A is reporting that above two erratum are missing to be enabled that's
why enable them by default.

For futher information please refer to
https

fix(versal): enable a72 erratum 859971 and 1319367

TF-A is reporting that above two erratum are missing to be enabled that's
why enable them by default.

For futher information please refer to
https://developer.arm.com/documentation/epm012079/11/

where
859971 is "Speculative instruction prefetch to Execute-never (XN) memory
could cause deadlock or data integrity issue" and
1319367 is "Speculative AT instruction using out-of-context translation
regime could cause subsequent request to generate an incorrect
translation".

Change-Id: I408706713a169e53db63ac5657751b0b003e646d
Signed-off-by: Michal Simek <michal.simek@amd.com>

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Merge "fix(mt8186): fix EMI_MPU domain setting for DSP" into integration

Merge "fix(rk3399): explicitly define the sys_sleep_flag_sram type" into integration

chore(rpi3): remove redundant code

The pwr_domain_pwr_down_wfi entry is overridden by a newer
implementation. This removes the last reference to
rpi3_pwr_domain_pwr_down_wfi. Remove both as they are

chore(rpi3): remove redundant code

The pwr_domain_pwr_down_wfi entry is overridden by a newer
implementation. This removes the last reference to
rpi3_pwr_domain_pwr_down_wfi. Remove both as they are not needed

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ie65c40935cd1ed3c673ffdc9aa72064f5ab4032e

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fix(rk3399): explicitly define the sys_sleep_flag_sram type

Recent GCC versions now do array-bounds checking which fails for
sys_sleep_flag_sram because the struct is larger than the 8-bytes
size th

fix(rk3399): explicitly define the sys_sleep_flag_sram type

Recent GCC versions now do array-bounds checking which fails for
sys_sleep_flag_sram because the struct is larger than the 8-bytes
size that (void *) is

This variable is only used in one place as the struct,
so it can be defined with the struct type.

Resolves:
plat/rockchip/px30/drivers/pmu/pmu.c: In function 'rockchip_soc_sys_pwr_dm_suspend':
plat/rockchip/px30/drivers/pmu/pmu.c:977:23: error: array subscript 'struct psram_data_t[0]' is partly outside array bounds of 'void[8]' [-Werror=array-bounds]
977 | psram_boot_cfg->pm_flag &= ~PM_WARM_BOOT_BIT;

Change-Id: Ifbe42d11d0c7875f6cb23dc0b7ffb3f3f90c55a8
Signed-off-by: Scott Parlane <scott@parlanenz.com>

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Merge "feat(cpu): add library support for Hunter ELP" into integration

fix(mt8186): fix EMI_MPU domain setting for DSP

Correct the domain setting for DSP. It should be 6.

BUG=b:249954378
TEST=audio is functional.

Change-Id: Ie79aa0dad3d2b1ef5de0f2acc51ded13b6f085ac
S

fix(mt8186): fix EMI_MPU domain setting for DSP

Correct the domain setting for DSP. It should be 6.

BUG=b:249954378
TEST=audio is functional.

Change-Id: Ie79aa0dad3d2b1ef5de0f2acc51ded13b6f085ac
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>

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feat(cpu): add library support for Hunter ELP

Add basic CPU library code to support the Hunter ELP CPU in TF-A.
Hunter-ELP adds v9.2 architecture support and is derived from
Makalu-ELP. As such, the

feat(cpu): add library support for Hunter ELP

Add basic CPU library code to support the Hunter ELP CPU in TF-A.
Hunter-ELP adds v9.2 architecture support and is derived from
Makalu-ELP. As such, the library code is adapted from the
Makalu-ELP support library.

Change-Id: I7e93b9af6b1f0bc4d08c3cf5caf071d2cbdbc89f
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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feat(tc): enable RSS backend based measured boot

Measurements taken during boot are stored in RSS.
These measurements are included in the platform
attestation token.

Change-Id: Iac3356f813fb4173156

feat(tc): enable RSS backend based measured boot

Measurements taken during boot are stored in RSS.
These measurements are included in the platform
attestation token.

Change-Id: Iac3356f813fb417315681c718839319832a76191
Signed-off-by: David Vincze <david.vincze@arm.com>
Signed-off-by: Tamas Ban <tamas.ban@arm.com>

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feat(tc): increase maximum BL1/BL2/BL31 sizes

The maximum size of BL1/BL2/BL31 is increased due to
the added new functionalities, such as RSS based
measured boot on TC2.

Change-Id: I939c7c3da6bf870

feat(tc): increase maximum BL1/BL2/BL31 sizes

The maximum size of BL1/BL2/BL31 is increased due to
the added new functionalities, such as RSS based
measured boot on TC2.

Change-Id: I939c7c3da6bf870db46b32cd2836c6737de278bb
Signed-off-by: David Vincze <david.vincze@arm.com>
Signed-off-by: Tamas Ban <tamas.ban@arm.com>

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fix(rss): rename AP-RSS message size macro

Adding PLAT_* prefix to indicate that the
platform needs to provide this definition.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I0bd02be405fd

fix(rss): rename AP-RSS message size macro

Adding PLAT_* prefix to indicate that the
platform needs to provide this definition.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I0bd02be405fd8b1e625bd2b82647ebb2b58265fc

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feat(tc): add RSS-AP message size macro

Define the RSS_COMMS_PAYLOAD_MAX_SIZE macro. Its value is platform
specific and gives the largest message size which are exchanged
on the TC2 platform between

feat(tc): add RSS-AP message size macro

Define the RSS_COMMS_PAYLOAD_MAX_SIZE macro. Its value is platform
specific and gives the largest message size which are exchanged
on the TC2 platform between RSS and AP.

Change-Id: Id831c282dc9a39755b82befead1a81767e217215
Signed-off-by: David Vincze <david.vincze@arm.com>
Signed-off-by: Tamas Ban <tamas.ban@arm.com>

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feat(tc): add MHU addresses for AP-RSS comms on TC2

Change-Id: I600485ca83f91378d07cac6cee484bc4a1bf2a9c
Signed-off-by: David Vincze <david.vincze@arm.com>

Merge changes from topic "mb/drtm-preparatory-patches" into integration

* changes:
docs(drtm): steps to run DRTM implementation
docs(drtm): add platform APIs for DRTM
feat(drtm): flush dcache

Merge changes from topic "mb/drtm-preparatory-patches" into integration

* changes:
docs(drtm): steps to run DRTM implementation
docs(drtm): add platform APIs for DRTM
feat(drtm): flush dcache before DLME launch
feat(drtm): invalidate icache before DLME launch
feat(drtm): ensure that passed region lies within Non-Secure region of DRAM
feat(fvp): add plat API to validate that passed region is non-secure
feat(drtm): ensure that no SDEI event registered during dynamic launch
feat(drtm): prepare EL state during dynamic launch
feat(drtm): prepare DLME data for DLME launch
feat(drtm): take DRTM components measurements before DLME launch
feat(drtm): add a few DRTM DMA protection APIs
feat(drtm): add remediation driver support in DRTM
feat(fvp): add plat API to set and get the DRTM error
feat(drtm): add Event Log driver support for DRTM
feat(drtm): check drtm arguments during dynamic launch
feat(drtm): introduce drtm dynamic launch function
refactor(measured-boot): split out a few Event Log driver functions
feat(drtm): retrieve DRTM features
feat(drtm): add platform functions for DRTM
feat(sdei): add a function to return total number of events registered
feat(drtm): add PCR entries for DRTM
feat(drtm): update drtm setup function
refactor(crypto): change CRYPTO_SUPPORT flag to numeric
feat(mbedtls): update mbedTLS driver for DRTM support
feat(fvp): add crypto support in BL31
feat(crypto): update crypto module for DRTM support
build(changelog): add new scope for mbedTLS and Crypto module
feat(drtm): add standard DRTM service
build(changelog): add new scope for DRTM service
feat(fvp): increase MAX_XLAT_TABLES entries for DRTM support
feat(fvp): increase BL31's stack size for DRTM support
feat(fvp): add platform hooks for DRTM DMA protection

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Merge "fix(qti): adding secure rm flag" into integration

fix(qti): adding secure rm flag

Adding SECURE rm flag to support INTR_EL3_VALID_RM1 routing model.

Signed-off-by: Muhammad Arsath K F <quic_mkf@quicinc.com>
Change-Id: Ie72d62148e81d3cf7fb05f46124f

fix(qti): adding secure rm flag

Adding SECURE rm flag to support INTR_EL3_VALID_RM1 routing model.

Signed-off-by: Muhammad Arsath K F <quic_mkf@quicinc.com>
Change-Id: Ie72d62148e81d3cf7fb05f46124f846cc45d9d41

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