Merge "fix(versal): initialize the variable with value 0 in pm code" into integration

fix(zynqmp): check return status of pm_get_api_version

MISRA Violation: MISRA C-2012 Rule 17.7
- Check the return status of function pm_get_api_version
and return error in case of failure.

Signed-o

fix(zynqmp): check return status of pm_get_api_version

MISRA Violation: MISRA C-2012 Rule 17.7
- Check the return status of function pm_get_api_version
and return error in case of failure.

Signed-off-by: Naman Patel <naman.patel@amd.com>
Change-Id: I69fb000c04f22996da7965a09a1797c7bfaad252

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fix(versal): initialize the variable with value 0 in pm code

Remove zeromem function as the array is already initialized
with value 0.

MISRA Violation: MISRA C-2012 Rule 9.1
- Initialize the array/

fix(versal): initialize the variable with value 0 in pm code

Remove zeromem function as the array is already initialized
with value 0.

MISRA Violation: MISRA C-2012 Rule 9.1
- Initialize the array/variable with a value 0 to resolve
the misra warnings in pm_service component.

Signed-off-by: Naman Patel <naman.patel@amd.com>
Change-Id: I1a3d44a7ae4088a3034eb0119d82b99cd4617ccd

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Merge "feat(qemu): increase size of bl2" into integration

feat(lx2): support more variants

Add more lx2 variants support.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Iac19b2532531616f638fd8f42bb6953bd1e83eda

fix(lx2): init global data before using it

Need to initialize global data firstly.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I18c3ccc2d0c8175bf479889aa03bc1f737df678b

fix(ls1046a): 4 keys secureboot failure resolved

Changed the size of OCRAM reserved by ROM code and increased the
size of CSF header.
Earlier, 4 keys image was exceeding boundaries and landing in
OC

fix(ls1046a): 4 keys secureboot failure resolved

Changed the size of OCRAM reserved by ROM code and increased the
size of CSF header.
Earlier, 4 keys image was exceeding boundaries and landing in
OCRAM location reserved for ROM usage.

Signed-off by:- Kshitiz Varshney <kshitiz.varshney@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I628ff7464fe0184d0553a7962d592aafd42e8137

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fix(intel): agilex bitstream pre-authenticate

HSD #15012010816: To add in bitstream pre-authentication checking.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Ia8f1471a674ba169729

fix(intel): agilex bitstream pre-authenticate

HSD #15012010816: To add in bitstream pre-authentication checking.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Ia8f1471a674ba16972927084f5fdc27c4ba93103

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fix(intel): mailbox store QSPI ref clk in scratch reg

When HPS requests QSPI controller access the SDM returns the QSPI
reference clock frequency. Store the provided reference clock frequency
(in kH

fix(intel): mailbox store QSPI ref clk in scratch reg

When HPS requests QSPI controller access the SDM returns the QSPI
reference clock frequency. Store the provided reference clock frequency
(in kHz) in BOOT_SCRATCH_COLD_0 register (bits [27:0]) as u-boot
QSPI driver expects this.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I6b95c19db602387a79ff10abdebbc57abb0c07ff

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fix(intel): remove checking on TEMP and VOLT checking for HWMON

Remove high level logic hardware channel checking on HWMON
TEMP and VOLT read.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
C

fix(intel): remove checking on TEMP and VOLT checking for HWMON

Remove high level logic hardware channel checking on HWMON
TEMP and VOLT read.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I9102b7b4334cb95f0b622c498a6569328f534d42

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fix(intel): fix sp_timer0 is not disabled in firewall on Agilex

sp_timer0 is not disabled in firewall on Agilex causing Zephyr is facing
issue to access the timer.

Signed-off-by: Jit Loon Lim <jit.

fix(intel): fix sp_timer0 is not disabled in firewall on Agilex

sp_timer0 is not disabled in firewall on Agilex causing Zephyr is facing
issue to access the timer.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I0099e200d6c9ca435f46393c6ed9cbe387870af0

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feat(intel): setup FPGA interface for Agilex

Enable/Disable FPGA interfaces based on handoff configuration.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I8667f362aa53e7c68723e0db

feat(intel): setup FPGA interface for Agilex

Enable/Disable FPGA interfaces based on handoff configuration.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I8667f362aa53e7c68723e0dbd5284844ae39dfb5

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fix(intel): fix pinmux handoff bug on Agilex

Incorrect number of FPGA pinmux registers was copied from handoff data.
This caused pinmux_emac0_usefpga register to always be zero meaning
"EMAC0 uses H

fix(intel): fix pinmux handoff bug on Agilex

Incorrect number of FPGA pinmux registers was copied from handoff data.
This caused pinmux_emac0_usefpga register to always be zero meaning
"EMAC0 uses HPS IO Pins" even if handoff data for this register was one
meaning "EMAC0 uses the FPGA Inteface".

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Ia0bd832c61d25f66ef13f39fe28b054cb96af9a1

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fix(intel): fix print out ERROR when encounter SEU_Err

Print out ERROR message when system face encounter SEU_ERR

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <

fix(intel): fix print out ERROR when encounter SEU_Err

Print out ERROR message when system face encounter SEU_ERR

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I744afbca23b74b164e47472039b5d6fbe5c3c764

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refactor(qemu): pass platform metadata as a function's argument

Based on the prototype modification of the event_log_measure_and_record
function in the previous patch, platform metadata was passed a

refactor(qemu): pass platform metadata as a function's argument

Based on the prototype modification of the event_log_measure_and_record
function in the previous patch, platform metadata was passed as an
argument.

Change-Id: I9d8316914c046f47cdc6875b16649479e82087aa
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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refactor(imx8m): pass platform metadata as a function's argument

Based on the prototype modification of the event_log_measure_and_record
function in the previous patch, platform metadata was passed

refactor(imx8m): pass platform metadata as a function's argument

Based on the prototype modification of the event_log_measure_and_record
function in the previous patch, platform metadata was passed as an
argument.

Change-Id: I4b98b6a035abb28c000344f2dbeb3996c69eee61
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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refactor(fvp): pass platform metadata as a function's argument

Based on the prototype modification of the event_log_measure_and_record
function in the previous patch, platform metadata was passed as

refactor(fvp): pass platform metadata as a function's argument

Based on the prototype modification of the event_log_measure_and_record
function in the previous patch, platform metadata was passed as an
argument.

Change-Id: Id1bf59c243c483d7e32152f094c693e95d29fe2b
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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fix(layerscape): fix nv_storage assert checking

Fix incorrect assert checking.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Ia963bfc053b578f0778ccf06d1dbc2ced4efc266

fix(layerscape): fix errata a008850

Remove errata a008850 from ls1028a and ls1088a, it should
only be feasible for ls1020a, ls1043a and ls1046a.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Chang

fix(layerscape): fix errata a008850

Remove errata a008850 from ls1028a and ls1088a, it should
only be feasible for ls1020a, ls1043a and ls1046a.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I8ab84158a2ed6bb15b16d10f8796c3e86fc560a5

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fix(intel): fix UART baud rate and clock

Revise the UART baud rate and clock for general platform build,
SIMIC build and EMU build.

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id:

fix(intel): fix UART baud rate and clock

Revise the UART baud rate and clock for general platform build,
SIMIC build and EMU build.

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I62fefe7b96d5124e75d2810b4fbc1640422b1353

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feat(qemu): increase size of bl2

Increases BL2 size to have room to enable security features (like
measurement and TPM).

Signed-off-by: Leo Yan <leo.yan@linaro.org>
Change-Id: Iba5e8923e2e154315499

feat(qemu): increase size of bl2

Increases BL2 size to have room to enable security features (like
measurement and TPM).

Signed-off-by: Leo Yan <leo.yan@linaro.org>
Change-Id: Iba5e8923e2e154315499e9bfce2e0aff0ccc8f95

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fix(qemu-sbsa): enable SVE and SME

Commit 337ff4f1dd6604738d79fd3fa275ae74d74256b2 enabled SVE/SME for
qemu platform. Let do the same for qemu-sbsa one too.

With this change I can boot Debian 'book

fix(qemu-sbsa): enable SVE and SME

Commit 337ff4f1dd6604738d79fd3fa275ae74d74256b2 enabled SVE/SME for
qemu platform. Let do the same for qemu-sbsa one too.

With this change I can boot Debian 'bookworm' installed using Max cpu.

Info from referenced commit:

Starting with QEMU v3.1.0 (Dec 2018), QEMU's TCG emulation engine supports
the SVE architecture extension. In QEMU v7.1.0 (Aug 2022) it also gained
SME support.

As it stands today, running TF-A under QEMU with "-cpu max" makes Linux
hang, because SME and SVE accesses trap to EL3, but are never handled
there. This is because the Linux kernel sees the SVE or SME feature bits,
and assumes firmware has enabled the feature for lower exception levels.
This requirement is described in the Linux kernel booting protocol.

Enable those features in the TF-A build, so that BL31 does the proper
EL3 setup to make the feature usable in non-secure world.
We check the actual feature bits before accessing SVE or SME registers,
so this is safe even for older QEMU version or when not running with
-cpu max. As SVE and SME are AArch64 features only, do not enable them
when building for AArch32.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I9ea1f91e6b801218d944e8a7d798d5ae568ed59a

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fix(zynqmp): resolve coverity warnings

Fix for coverity issues in pm_service component.
Fixed compilation error for versal platform.

Change-Id: I948f01807e67ad1e41021557e040dcbfb7b3a39e
Signed-off-

fix(zynqmp): resolve coverity warnings

Fix for coverity issues in pm_service component.
Fixed compilation error for versal platform.

Change-Id: I948f01807e67ad1e41021557e040dcbfb7b3a39e
Signed-off-by: HariBabu Gattem <haribabu.gattem@amd.com>
Signed-off-by: Naman Patel <naman.patel@amd.com>

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fix(rockchip): align fdt buffer on 8 bytes

Since commit 94b2f94bd632 ("feat(libfdt): upgrade libfdt source files"),
8-byte alignment of the FDT address is enforced to follow the DT
standard.

Rockch

fix(rockchip): align fdt buffer on 8 bytes

Since commit 94b2f94bd632 ("feat(libfdt): upgrade libfdt source files"),
8-byte alignment of the FDT address is enforced to follow the DT
standard.

Rockchip implementation of params_early_setup loads the FDT address as
passed by the bootloader into a buffer. This buffer is currently made of
uint8_t which means it is not 8-byte aligned and might result in
fdt_open_into failing.

Instead, let's make this buffer uint64_t to make it 8-byte aligned.

Cc: Quentin Schulz <foss+tf-a@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Change-Id: Ifcf0e0cf4000e3661d76d3c3a2fe3921f7fe44b9

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refactor(stm32mp1): remove STM32MP_USE_STM32IMAGE

The code managing legacy boot (without FIP) that was under
STM32MP_USE_STM32IMAGE flag is remove.

Change-Id: I04452453ed84567b0de39e900594a81526562

refactor(stm32mp1): remove STM32MP_USE_STM32IMAGE

The code managing legacy boot (without FIP) that was under
STM32MP_USE_STM32IMAGE flag is remove.

Change-Id: I04452453ed84567b0de39e900594a81526562259
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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