Merge "feat(zynqmp): add SMCCC_ARCH_SOC_ID support" into integration

feat(qemu): combine TF-A artefacts into ROM file

At the moment the QEMU platform documentation asks users to combine
bl1.bin and fip.bin in a certain way to get an image that can be used on
the QEMU

feat(qemu): combine TF-A artefacts into ROM file

At the moment the QEMU platform documentation asks users to combine
bl1.bin and fip.bin in a certain way to get an image that can be used on
the QEMU command line.

Let the build system actually create those files already, if we provide
a non-secure payload (BL33), to simplify deployment and spare the user of
fragile operations.

Change-Id: Ia35f17b9d60aab41f0d53f1f73a1326a316c4950
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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fix(zynqmp): fix DT reserved allocated size

BL31_LIMIT is not size but reserved node reg property contains base
address and size that's why BL31_LIMIT - BL31_BASE + 1 is correct size
of reseved spac

fix(zynqmp): fix DT reserved allocated size

BL31_LIMIT is not size but reserved node reg property contains base
address and size that's why BL31_LIMIT - BL31_BASE + 1 is correct size
of reseved space for BL31.
Also update warning message to cover that it is for BL31.

Change-Id: I53f53d2170eb873f758f9ba250d54f57f0b562b4
Signed-off-by: Michal Simek <michal.simek@amd.com>

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build: permit multiple linker scripts

This change allows platforms to provide more than one linker script to
any image utilizing the `MAKE_BL` build system macro.

This is already done by some Media

build: permit multiple linker scripts

This change allows platforms to provide more than one linker script to
any image utilizing the `MAKE_BL` build system macro.

This is already done by some MediaTek platforms via the
`EXTRA_LINKERFILE` build system variable, which has now been removed.

In its place, additional linker scripts may be added to the
`<IMAGE>_LINKER_SCRIPT_SOURCES` variable.

BREAKING-CHANGE: The `EXTRA_LINKERFILE` build system variable has been
replaced with the `<IMAGE>_LINKER_SCRIPT_SOURCES` variable. See the
commit message for more information.

Change-Id: I3f0b69200d6a4841fd158cd09344ce9e67047271
Signed-off-by: Chris Kay <chris.kay@arm.com>

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build: clarify linker script generation

The following build system variables have been renamed:

- `LINKERFILE` -> `DEFAULT_LINKER_SCRIPT`
- `BL_LINKERFILE` -> `DEFAULT_LINKER_SCRIPT_SOURCE`
- `<IMA

build: clarify linker script generation

The following build system variables have been renamed:

- `LINKERFILE` -> `DEFAULT_LINKER_SCRIPT`
- `BL_LINKERFILE` -> `DEFAULT_LINKER_SCRIPT_SOURCE`
- `<IMAGE>_LINKERFILE` -> `<IMAGE>_DEFAULT_LINKER_SCRIPT_SOURCE`

These new names better reflect how each variable is used:

1. the default linker script is passed via `-dT` instead of `-T`
2. linker script source files are first preprocessed

Additionally, linker scripts are now placed in the build directory
relative to where they exist in the source directory. For example,
the `bl32/sp_min/sp_min.ld.S` would now preprocess to
`sp_min/sp_min.ld` instead of just `bl32.ld`

BREAKING-CHANGE: The `LINKERFILE`, `BL_LINKERFILE` and
`<IMAGE_LINKERFILE>` build system variables have been renamed. See the
commit message for more information.

Change-Id: If8cef65dcb8820e8993736702c8741e97a66e6cc
Signed-off-by: Chris Kay <chris.kay@arm.com>

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Merge changes from topic "mb/tos-fw-config-load-refactor" into integration

* changes:
feat(spmd): map SPMC manifest region as EL3_PAS
feat(fvp): update device tree with load addresses of TOS_FW

Merge changes from topic "mb/tos-fw-config-load-refactor" into integration

* changes:
feat(spmd): map SPMC manifest region as EL3_PAS
feat(fvp): update device tree with load addresses of TOS_FW config
refactor(fvp): rename the DTB info structure member
feat(fconf): rename 'ns-load-address' to 'secondary-load-address'

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fix(zynqmp): enable A53 workaround(errata 1530924)

BL31 already reports that there is missing CPU workaround for this
erratum as
"WARNING: BL31: cortex_a53: CPU workaround for 1530924 was missing!"

fix(zynqmp): enable A53 workaround(errata 1530924)

BL31 already reports that there is missing CPU workaround for this
erratum as
"WARNING: BL31: cortex_a53: CPU workaround for 1530924 was missing!"

That's why enable it by default as was done by other platforms for
example by commit 74665119f04d ("allwinner: Enable workaround for
Cortex-A53 erratum 1530924").

Change-Id: I251ffe3c307781b07477afb64f4e7af5dd9af9fe
Signed-off-by: Michal Simek <michal.simek@amd.com>

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feat(zynqmp): add SMCCC_ARCH_SOC_ID support

Add support for calling SMCCC_ARCH_SOC_ID which is used by Linux soc_id
driver for printing information about manufacturer and also chip version
and silic

feat(zynqmp): add SMCCC_ARCH_SOC_ID support

Add support for calling SMCCC_ARCH_SOC_ID which is used by Linux soc_id
driver for printing information about manufacturer and also chip version
and silicon ID code. SOC revision is directly mapped to chip ID code.
And SOC version is composed from manufacturer ID based on JEP-106 with
chip_id which contains bits mapped to CPU register 0xffca0044 platform
bits which differentiate between silicon, qemu and other emulated
platforms.

Function description is available at
docs/getting_started/porting-guide.rst.

Change-Id: I1f19e1973593897e71b39244dbdbceb6bd0e8a07
Signed-off-by: Michal Simek <michal.simek@amd.com>

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Merge changes I7bd311d7,Iea7dcfe3,I9d890934 into integration

* changes:
refactor(allwinner): use fdt_node_is_enabled() in AXP driver
fix(allwinner): check RSB availability in DT on H6
refactor

Merge changes I7bd311d7,Iea7dcfe3,I9d890934 into integration

* changes:
refactor(allwinner): use fdt_node_is_enabled() in AXP driver
fix(allwinner): check RSB availability in DT on H6
refactor(fdt): introduce common fdt_node_is_enabled()

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feat(spmd): map SPMC manifest region as EL3_PAS

Mapped SPMC manifest region as EL3_PAS so that it will get
mapped as Root region in RME enabled system otherwise Secure
region.

Change-Id: I1af5344d7

feat(spmd): map SPMC manifest region as EL3_PAS

Mapped SPMC manifest region as EL3_PAS so that it will get
mapped as Root region in RME enabled system otherwise Secure
region.

Change-Id: I1af5344d7516e948d5b3664bcdb94cdfc367cd78
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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feat(fvp): update device tree with load addresses of TOS_FW config

Provided both the root and secure addresses for TOS_FW config
in case of RME enabled systems where root address is in Root
SRAM and

feat(fvp): update device tree with load addresses of TOS_FW config

Provided both the root and secure addresses for TOS_FW config
in case of RME enabled systems where root address is in Root
SRAM and secure address is in Trusted DRAM.

Non-RME systems are unaffected by this change.

Change-Id: Ifb927c90fa5a68fe5362980858b4ddc5403ac95b
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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refactor(fvp): rename the DTB info structure member

In line with the previous patch, the name of the member of the
hw_config DTB info structure has been renamed.

Change-Id: I6689e416fecd66faa515e82

refactor(fvp): rename the DTB info structure member

In line with the previous patch, the name of the member of the
hw_config DTB info structure has been renamed.

Change-Id: I6689e416fecd66faa515e820f1c4b23bcb65bfb1
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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refactor(fiptool): move plat_fiptool.mk to tools

Move all plat_fiptool.mks into tools, change the logic to recursively
check for tools/fiptool/plat_fiptool/<plat_path>/plat_fiptool.mk

I.e. for a pl

refactor(fiptool): move plat_fiptool.mk to tools

Move all plat_fiptool.mks into tools, change the logic to recursively
check for tools/fiptool/plat_fiptool/<plat_path>/plat_fiptool.mk

I.e. for a platform that has the path "plat/arm/board/tc/platform.mk",
the makefile will now load the first existing file from:
- tools/fiptool/plat_fiptool/arm/board/tc/plat_fiptool.mk
- tools/fiptool/plat_fiptool/arm/board/plat_fiptool.mk
- tools/fiptool/plat_fiptool/arm/plat_fiptool.mk

This enables fiptool to support multiple platforms, or a specific one.

Remove file-copying previously being used to handle old default path.
Remove custom file cleaning in plat_fiptool.mk.

Change-Id: I95245bcf7143b329481d4394ab64f29bfe9de5ab
Signed-off-by: Raef Coles <raef.coles@arm.com>

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fix(allwinner): check RSB availability in DT on H6

At the moment we access the RSB bus on all Allwinner H6 boards
unconditionally, even though some boards do not have any PMIC at all,
while others h

fix(allwinner): check RSB availability in DT on H6

At the moment we access the RSB bus on all Allwinner H6 boards
unconditionally, even though some boards do not have any PMIC at all,
while others have some I2C devices connected to the same pins.
The latter case is just fragile, but the first case leads to a hang on
at least one board, as reported by Jernej.

Scan the devicetree, to check for the availability of the RSB bus node.
Proceed only if the RSB DT node is actually enabled.

Change-Id: Iea7dcfe3e085e173334d098ec4ddcb6c4b085771
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reported-by: Jernej Skrabec <jernej.skrabec@gmail.com>

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refactor(fdt): introduce common fdt_node_is_enabled()

There are several users in the tree which want to check whether a given
FDT node is enabled or not: the "status" property holds that
information

refactor(fdt): introduce common fdt_node_is_enabled()

There are several users in the tree which want to check whether a given
FDT node is enabled or not: the "status" property holds that
information. So far all those users provide private implementations,
some of them having issues.

Export a generic implementation of that function in fdt_wrappers.h, as
a "static inline" function to not increase code size.
Also replace the existing implementation in Arm's fconf code, which had
a tiny bug in needlessly using the property length:
"status = [6f 6b 61 79 20];" would pass the check, where it should not.
The proper solution is also simpler: status must be a string, and
strings must be NUL-terminated in a DT. strcmp() would terminate on the
first NUL in *either* of the two strings it compares, so it would never
walk beyond the property boundary in the DTB.

Change-Id: I9d89093432f127c09add6cf5c93a725bc534e5de
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge "fix(versal-net): populate gic v3 rdist data statically" into integration

Merge changes from topic "xlnx_feat_chores" into integration

* changes:
chore(xilinx): update print information
feat(versal-net): add jtag dcc support

chore(xilinx): update print information

Remove company name from the console messages while printing only
relevant information for the platform.

Change-Id: Id8171326e0267eb6f3a26de4eb66143970de2dbd

chore(xilinx): update print information

Remove company name from the console messages while printing only
relevant information for the platform.

Change-Id: Id8171326e0267eb6f3a26de4eb66143970de2dbd
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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Merge changes I1b092bc1,Ifc2461b4,I5176caa5 into integration

* changes:
docs(rme): update RMM-EL3 Boot Manifest structure description
feat(rme): read DRAM information from FVP DTB
feat(rme): s

Merge changes I1b092bc1,Ifc2461b4,I5176caa5 into integration

* changes:
docs(rme): update RMM-EL3 Boot Manifest structure description
feat(rme): read DRAM information from FVP DTB
feat(rme): set DRAM information in Boot Manifest platform data

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fix(versal-net): populate gic v3 rdist data statically

Currently gicv3_rdistif_probe() is called per CPU. In case of maxcpus=1,
only 1 core is initialized and gicr_base_addrs initialized for CPU 0
o

fix(versal-net): populate gic v3 rdist data statically

Currently gicv3_rdistif_probe() is called per CPU. In case of maxcpus=1,
only 1 core is initialized and gicr_base_addrs initialized for CPU 0
only. Because of this assertion is raised during Linux system suspend.

During Linux suspend, platform callback saves GIC v3 state which
internally invokes arm_gicv3_distif_pre_save(). This function tries to use
gicr_base for all CPUs. Since GICR base address for secondary CPUs are not
initialized, it raises assertion.

To fix the issue, populate GIC v3 rdist data statically (similar to Versal)
instead of dynamically initializing GIC v3 rdist per CPU.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I98c97c03e451d05f4ebac358e197617ab9d9b71f

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feat(versal-net): add jtag dcc support

Add support for JTAG Debug Communication Channel(DCC), using the dcc
console driver, for Versal NET platform.
UART0/UART1 is not configured when the JTAG DCC i

feat(versal-net): add jtag dcc support

Add support for JTAG Debug Communication Channel(DCC), using the dcc
console driver, for Versal NET platform.
UART0/UART1 is not configured when the JTAG DCC is used as console for
the platform.
Though DCC is not using any UART, VERSAL_NET_UART_BASE needs
to be defined in the platform code. If its not defined, build errors
are observed.
Now VERSAL_NET_UART_BASE by default points to UART0 base.
Check for valid console(pl011, pl011_0, pl011_1, dcc) is
being done in the platform makefile, the error condition in
setting the value of VERSAL_NET_UART_BASE is redundant, thus the error
message is removed from the code.

Change-Id: I1085433055abea13526230cff4d4183ff7a01477
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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feat(rme): read DRAM information from FVP DTB

This patch builds on the previous patch by implementing
support for reading NS DRAM layout of FVP model from
HW_CONFIG Device tree.

Macro _RMMD_MANIFES

feat(rme): read DRAM information from FVP DTB

This patch builds on the previous patch by implementing
support for reading NS DRAM layout of FVP model from
HW_CONFIG Device tree.

Macro _RMMD_MANIFEST_VERSION is renamed to
SET_RMMD_MANIFEST_VERSION to suppress MISRA-C
"rule MC3R1.D4.5: (advisory) Identifiers in
the same name space with overlapping visibility
should be typographically unambiguous" warning

Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
Change-Id: Ifc2461b4441a1efdd4b7c656ab4d15e62479f77b

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Merge "feat(morello): add support for HW_CONFIG" into integration

perf(imx): speed-up console/uart TX using FIFO

The current putc version test for TXEMPTY bit set (#6) instead
of waiting for TXFULL bit clear (#4), that slows the global
boot time as we are not taki

perf(imx): speed-up console/uart TX using FIFO

The current putc version test for TXEMPTY bit set (#6) instead
of waiting for TXFULL bit clear (#4), that slows the global
boot time as we are not taking benefit of the 32-byte FIFO.

We then need to implement the flush function to be sure the
transmit is complete (FIFO and shift register empty).

Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Change-Id: I54873a5203e2afdc230e44ce73284e7a80985b4f

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feat(morello): add support for HW_CONFIG

This patch add support to load HW_CONFIG in BL2 and pass it to
bootloader stages BL31 and BL33.

Signed-off-by: Patrik Berglund <patrik.berglund@arm.com>
Cha

feat(morello): add support for HW_CONFIG

This patch add support to load HW_CONFIG in BL2 and pass it to
bootloader stages BL31 and BL33.

Signed-off-by: Patrik Berglund <patrik.berglund@arm.com>
Change-Id: I646fabed83dbca5322a59a399de5194cfef474ad

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