fix(versal2): move plat_core_pos_by_mpidr to asm

In the current implementation, plat_core_pos_by_mpidr() is defined in
C.When BL31 is compiled with Armclang, a call to plat_core_pos_by_mpidr()
from

fix(versal2): move plat_core_pos_by_mpidr to asm

In the current implementation, plat_core_pos_by_mpidr() is defined in
C.When BL31 is compiled with Armclang, a call to plat_core_pos_by_mpidr()
from plat_my_core_pos() results in the return address stored in register
x30 becoming invalid and register x9 (used later) ends up with the value
0x0. Consequently, the CPU branches to address 0x0, triggering a
synchronous exception. TF-A then invokes the BHB flush code before
resuming execution. However, since the stack is not properly initialized
at this stage, the system eventually enters plat_panic_handler().
In the updated implementation, the platform_get_core_pos() function
is redefined in assembly to provide tighter control during early boot
stages. The MPIDR_EL1 register contains three affinity levels: Aff0
(bits [0:7]), Aff1 (bits [8:15]), and Aff2 (bits [16:23]). In this
assembly function, the core ID is extracted from Aff1
(MPIDR_AFF1_SHIFT), and the cluster ID from Aff2 (MPIDR_AFF2_SHIFT).
cluster/core ID calculation. The macro PLATFORM_MPIDR_AFFINITY_MASK
introduced to mask MPIDR_EL1 register.

Change-Id: Id532bbcd68f18e87ceba01c8f961d8c15962a1a3
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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fix(versal-net): move plat_core_pos_by_mpidr to asm

In the current implementation, plat_core_pos_by_mpidr() is defined
in C. When BL31 is compiled with Armclang, a call to
plat_core_pos_by_mpidr() f

fix(versal-net): move plat_core_pos_by_mpidr to asm

In the current implementation, plat_core_pos_by_mpidr() is defined
in C. When BL31 is compiled with Armclang, a call to
plat_core_pos_by_mpidr() from plat_my_core_pos() results in the
return address stored in register x30 becoming invalid and register
x9 (used later) ends up with the value 0x0. Consequently, the CPU
branches to address 0x0, triggering a synchronous exception. TF-A
then invokes the BHB flush code before resuming execution. However,
since the stack is not properly initialized at this stage, the system
eventually enters plat_panic_handler(). In the updated implementation,
the platform_get_core_pos() function is redefined in assembly to
provide tighter control during early boot stages. The MPIDR_EL1
register contains three affinity levels: Aff0 (bits [0:7]), Aff1
(bits [8:15]), and Aff2 (bits [16:23]). In this assembly function,
the core ID is extracted from Aff1 (MPIDR_AFF1_SHIFT), and the cluster
ID from Aff2 (MPIDR_AFF2_SHIFT). The macro PLATFORM_MPIDR_AFFINITY_MASK
introduced to mask MPIDR_EL1 register.

Change-Id: I090ea107c27dfa643431a97d15556c98f721b2e4
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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feat(mt8189): add SPM low power mode

1. Add enable PERI AO.
2. Add infra bus parity re-init.
3. SPM enter 26M.

Signed-off-by: Kun Lu <kun.lu@mediatek.com>
Change-Id: Ifbc2d87be47f106857db17c23fb968

feat(mt8189): add SPM low power mode

1. Add enable PERI AO.
2. Add infra bus parity re-init.
3. SPM enter 26M.

Signed-off-by: Kun Lu <kun.lu@mediatek.com>
Change-Id: Ifbc2d87be47f106857db17c23fb968aafec150d2

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Merge "fix(versal): update integer const with suffix U" into integration

feat(mt8189): add UFS driver support

Add UFS driver support in platform.mk.

Signed-off-by: Cloud Zhang <cloud.zhang@mediatek.corp-partner.google.com>
Change-Id: I1e816dc9c21e856ae50d4409f13b1a8598b

feat(mt8189): add UFS driver support

Add UFS driver support in platform.mk.

Signed-off-by: Cloud Zhang <cloud.zhang@mediatek.corp-partner.google.com>
Change-Id: I1e816dc9c21e856ae50d4409f13b1a8598b6fb3f

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fix(mediatek): fix mtcmos build failure

Fix mtcmos build failure due to lack of definition:
plat/mediatek/drivers/mtcmos/mtcmos_common.h:16:9:
error: unknown type name 'uint32_t'
plat/mediatek/drive

fix(mediatek): fix mtcmos build failure

Fix mtcmos build failure due to lack of definition:
plat/mediatek/drivers/mtcmos/mtcmos_common.h:16:9:
error: unknown type name 'uint32_t'
plat/mediatek/drivers/mtcmos/mt8189/mtcmos.h:31:41:
error: implicit declaration of function 'BIT'

Signed-off-by: irving-ch-lin <irving-ch.lin@mediatek.com>
Change-Id: I6550f2b99d43c72471d481eff081affe098144dd

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Merge changes from topic "Add-i.MX94/95-suport" into integration

* changes:
docs(maintainers): add i.MX9 to maintained paths
feat(imx94): add initial support for imx94
feat(imx95): add optee s

Merge changes from topic "Add-i.MX94/95-suport" into integration

* changes:
docs(maintainers): add i.MX9 to maintained paths
feat(imx94): add initial support for imx94
feat(imx95): add optee support
feat(imx95): support trusty os
feat(imx95): implement a semaphore for GIC quiescing
feat(imx95): add initial support for i.MX95
feat(imx9): add necessary ele api call support
feat(imx9): add imx9 common code base
refactor(imx): drop the __dead2 attribute
fix(imx): add static attribute for platform specific gic struct
feat(gic): change gic_cpuif_enable/disable to weak
feat(scmi): add i.MX9 SCMI vendor CPU protocol
feat(scmi): add base protocol agent API
feat(scmi): update version to 3.0
build(changelog): update for imx94/95 support

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fix(versal): update integer const with suffix U

Versal: standardize unsigned integer constants to use suffix.
Updated all unsigned integer constants in the Versal platform
to use the unsigned suffix

fix(versal): update integer const with suffix U

Versal: standardize unsigned integer constants to use suffix.
Updated all unsigned integer constants in the Versal platform
to use the unsigned suffix (e.g., `10U`)
instead of the prefix style (e.g., `U(10)`) for consistency.

Change-Id: Ie4d20c18cccede20062d6189c1024acfb3a3dce0
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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Merge changes from topic "xlnx_runtime_console" into integration

* changes:
fix(versal2): runtime console in debug mode
fix(versal-net): runtime console in debug mode
fix(versal): runtime cons

Merge changes from topic "xlnx_runtime_console" into integration

* changes:
fix(versal2): runtime console in debug mode
fix(versal-net): runtime console in debug mode
fix(versal): runtime console in debug mode
fix(zynqmp): runtime console in debug mode

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Merge "fix(versal-net): add fallback on handoff failure" into integration

Merge "fix(intel): add missing cache flush operation for hmac" into integration

fix(neoverse-rd): add console initialisation to BL31

Neoverse-RD currently neglects to initialise the console in BL31. This
change adds the missing initialisation routine.

Change-Id: I946485f4dd857

fix(neoverse-rd): add console initialisation to BL31

Neoverse-RD currently neglects to initialise the console in BL31. This
change adds the missing initialisation routine.

Change-Id: I946485f4dd857240208653e237a83e71073c33ff
Signed-off-by: Chris Kay <chris.kay@arm.com>

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fix(arm): re-enable console by default in BL31

In c997a8d, the common `arm_bl31_early_platform_setup` function
underwent a consolidation of two large preprocessor branches that were
conditional on w

fix(arm): re-enable console by default in BL31

In c997a8d, the common `arm_bl31_early_platform_setup` function
underwent a consolidation of two large preprocessor branches that were
conditional on whether or not Transfer List support is enabled.

This function would initialise the console via `arm_console_boot_init`
*only* if Transfer List support was disabled. During the consolidation,
this call was removed, such that the behaviour was the same for both
branches.

However, the common `bl31_early_platform_setup2` implementation was not
updated to reflect this change, and so platforms that a) relied on this
common implementation and b) did not enable Transfer List support no
longer initialise the console in BL31.

This change ensures that the common implementation correctly initialises
the console during early BL31 boot.

Change-Id: I332af3932ac70382fbf7a5434c0008807f38f86c
Signed-off-by: Chris Kay <chris.kay@arm.com>

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Merge "fix(intel): iossm v2 enhancement refactor" into integration

Merge "feat(mt8189): add thermal driver support" into integration

feat(versal2): remove handoff entry from tl

In Versal Gen 2, handoff passing mechanism is via transfer list.
Transfer list is packaged with handoff addresses of BL32, BL33 along
with DT blob as part

feat(versal2): remove handoff entry from tl

In Versal Gen 2, handoff passing mechanism is via transfer list.
Transfer list is packaged with handoff addresses of BL32, BL33 along
with DT blob as part of it.
Once TF-A process the hand off details, rest of the components
(primarily U-Boot) should not parse these details at non-secure world.

Post retrieval of handoff information, remove entry point structures
catering to OP-TEE and U-Boot.

Change-Id: Ia5ace44de68721dc73f29a07b1e79a9c97e4122a
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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fix(mt8189): remove unused SPM definitions and files

Remove unused SPM definitions and files to fix the coverity failure.

1. Remove PMIC_GS_DUMP_VER.
2. Remove CONFIG_MTK_VCOREDVFS_SUPPOR

Signed-o

fix(mt8189): remove unused SPM definitions and files

Remove unused SPM definitions and files to fix the coverity failure.

1. Remove PMIC_GS_DUMP_VER.
2. Remove CONFIG_MTK_VCOREDVFS_SUPPOR

Signed-off-by: Kun Lu <kun.lu@mediatek.com>
Change-Id: I61ff4aa847bf1399b080a3c6ddecf0e3cdcbd724

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fix(intel): correct condition to process unused entries

A logic error in the response queue handling caused available
entries to be skipped after an upstream change inverted the
flag check. This fix

fix(intel): correct condition to process unused entries

A logic error in the response queue handling caused available
entries to be skipped after an upstream change inverted the
flag check. This fix restores the intended logic so that unused
response slots are correctly detected and processed.

Change-Id: I253f098573c3c84dc43f48cff893c410684322a2
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): iossm v2 enhancement refactor

This patch is to used to update iossm v2 enhancement.
The major change is to replace io_mb_req to
mmio_read.
Next is to refactor the code.

Change-Id: Id084

fix(intel): iossm v2 enhancement refactor

This patch is to used to update iossm v2 enhancement.
The major change is to replace io_mb_req to
mmio_read.
Next is to refactor the code.

Change-Id: Id0842392f362e30252f1ac9f32797d8d3a419997
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(drtm): remove plat_system_reset()

The name plat_system_reset() has been in use for some time by a mediatek
platform (in plat/mediatek/mt8173/plat_pm.c). However, DRTM added a
global hook, that i

fix(drtm): remove plat_system_reset()

The name plat_system_reset() has been in use for some time by a mediatek
platform (in plat/mediatek/mt8173/plat_pm.c). However, DRTM added a
global hook, that is only implemented on FVP, that conflicts with it.
This sometimes results in failed builds.

DRTM remediation ends with a platform reset. However, there is currently
an error message printed that this is not supported. In this case, the
correct thing to do is to panic and as such this hook is not needed.

Further, the correct sequence to reset the system is different and is
only fully implemented by psci_system_reset(). This is a portable
implementation supported by a wide variety of platform.

So remove plat_system_reset(). Once DRTM remediation properly supports
resetting, the psci_system_reset() function should be used to achieve
reset correctly and portably.

Change-Id: Ia4e150c51aeec613838464fbb0e1d0542f19ccab
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(intel): add missing cache flush operation for hmac

Add missing cache flush operation for HMAC verify
operation.Also update the code to query the correct
buffer for the final result of HMAC veri

fix(intel): add missing cache flush operation for hmac

Add missing cache flush operation for HMAC verify
operation.Also update the code to query the correct
buffer for the final result of HMAC verify operation.

Change-Id: I85208765313b9048cfef13727d280dca8af6d548
Signed-off-by: Mahesh Rao <mahesh.rao@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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Merge "fix(intel): select the DFI interface based on the hand-off data" into integration

Merge "fix(intel): set BIT2 of system manager MPFE Interface Select" into integration

Merge "fix(intel): flush the mailbox response buffer in SiPSVC V3" into integration

fix(versal2): runtime console in debug mode

Whenever DEBUG is set to 1, the Makefile forces CONSOLE_RUNTIME to
pl011, regardless of the user-specified CONSOLE value. This causes a
build requested wi

fix(versal2): runtime console in debug mode

Whenever DEBUG is set to 1, the Makefile forces CONSOLE_RUNTIME to
pl011, regardless of the user-specified CONSOLE value. This causes a
build requested with CONSOLE=pl011_1 to register both pl011_1 and
pl011 as boot and runtime consoles. If the hardware is connected only
to UART1, this causes TF-A to hang when UART0 is selected as the
runtime console, since it waits indefinitely on the transmit FIFO.
The fix ensures that, in a DEBUG build, CONSOLE_RUNTIME defaults to
the same value as CONSOLE.

Change-Id: I2e29d5b77c43aa65f58224d226683f4a8d94271a
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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