feat(xilinx): deprecate PM_REQ_SUSPEND EEMI API

Deprecate the use of the PM_REQ_SUSPEND EEMI API from the Versal,
Versal-Net and Versal Gen 2 platforms. This is because the API is
intended for suspe

feat(xilinx): deprecate PM_REQ_SUSPEND EEMI API

Deprecate the use of the PM_REQ_SUSPEND EEMI API from the Versal,
Versal-Net and Versal Gen 2 platforms. This is because the API is
intended for suspending cross-subsystems, and the same functionality
can now be achieved using the ForcePowerdown API. Therefore,
continuing to use PM_REQ_SUSPEND API may no longer be necessary.
Hence deprecating the same.

Change-Id: I967d7803da4cf433fabfe8d87c32305954f69884
Signed-off-by: Ronak Jain <ronak.jain@amd.com>

show more ...

feat(cpufeat): enable FEAT_CPA2 for EL3

FEAT_CPA2 enables checked pointer arithmetic, which in the event
of an arithmetic overflow in pointer generation will result in a
non-canonical pointer being

feat(cpufeat): enable FEAT_CPA2 for EL3

FEAT_CPA2 enables checked pointer arithmetic, which in the event
of an arithmetic overflow in pointer generation will result in a
non-canonical pointer being generated and subsequent address fault.

Note that FEAT_CPA is a trivial implementation that exists in
some hardware purely so it can run CPA2-enabled instructions
without crashing but they don't actually have checked arithmetic,
so FEAT_CPA is not explicitly enabled in TF-A.

Change-Id: I6d2ca7a7e4b986bb9e917aa8baf8091a271c168b
Signed-off-by: John Powell <john.powell@arm.com>

show more ...

feat(ti): de-assert AINACTS at boot

De-asserting AINACTS at startup to enable ACP interface. This is
required to enable limited system level IO coherency via ACP port
(eg.: DMA traffic on AM62L driv

feat(ti): de-assert AINACTS at boot

De-asserting AINACTS at startup to enable ACP interface. This is
required to enable limited system level IO coherency via ACP port
(eg.: DMA traffic on AM62L driving ASEL = 14/15).

Change-Id: Iceaf992dec5dc37eae6dc06895585ea712f23496
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

show more ...

feat(arm): handle RMM ep_info during LFA

Update the logic for next image handoff to correctly manage the
RMM entry point information when LFA is in progress.
This ensures control is passed back into

feat(arm): handle RMM ep_info during LFA

Update the logic for next image handoff to correctly manage the
RMM entry point information when LFA is in progress.
This ensures control is passed back into RMM during the
activation sequence.

This change only affects during LFA run, normal boot behavior
is unchanged.

Change-Id: I8f85e9a7e0a7e9dab196c69ecf55abb9e7717982
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

show more ...

Merge "refactor(tc): neaten platform code after TC2 removal" into integration

refactor(arm): refine FIP offset handling for BL1 with GPT support

Restrict use of PLAT_ARM_FIP_OFFSET_IN_GPT to BL1 when ARM_GPT_SUPPORT
is enabled. BL2 can derive the FIP offset from the partition

refactor(arm): refine FIP offset handling for BL1 with GPT support

Restrict use of PLAT_ARM_FIP_OFFSET_IN_GPT to BL1 when ARM_GPT_SUPPORT
is enabled. BL2 can derive the FIP offset from the partition table at
runtime, so a fixed offset is unnecessary. Also cleaned up the FIP
address handling comment for clarity.

Change-Id: I03f003a9307d66d16666eefcff1f45bb010779c9
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

show more ...

fix: remove unused cpu_data related macros

There are no uses for CPU_DATA_PSCI_LOCK_OFFSET so it is removed.

PLAT_PCPU_DATA_SIZE is also unused in ST platforms and causes offsets
to mismatch when t

fix: remove unused cpu_data related macros

There are no uses for CPU_DATA_PSCI_LOCK_OFFSET so it is removed.

PLAT_PCPU_DATA_SIZE is also unused in ST platforms and causes offsets
to mismatch when the linker garbage collects it. It is also removed.

CPU_DATA_PLAT_PCPU_OFFSET is also removed as its only use is in
rcar_lock_get() and related macros which are never called since all
calls of these macros lack an argument.

Change-Id: I883ab58c56b4082e0e8b19a8d8f6186945bcc58e
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

show more ...

refactor(tc): neaten platform code after TC2 removal

Now that TC2 has been removed, the only TC platforms
are TC3 and TC4. Therefore, it no longer makes sense
to have both tc-base and tc3-4-base dts

refactor(tc): neaten platform code after TC2 removal

Now that TC2 has been removed, the only TC platforms
are TC3 and TC4. Therefore, it no longer makes sense
to have both tc-base and tc3-4-base dtsi files.
This patch combines the two base TC dtsi files,
and removes tautological ifdefs in TC platform code.

Change-Id: I011b5fe1f645d6d53276007b11a17bd6cf952ecb
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

show more ...

Merge changes from topic "ja/ffa_v1_3" into integration

* changes:
feat(tc): bump SPMC version to FF-A v1.3 TC platform
feat(fvp): bump the SPMC version
feat(ff-a): bump SPMD FF-A version

fix(cm): deprecate use of NS_TIMER_SWITCH

On AArch64, secure world has it's own EL3 physical timer registers
accessible to secure EL1 in absence of S-EL2. With S-EL2 there is
virtualized view availa

fix(cm): deprecate use of NS_TIMER_SWITCH

On AArch64, secure world has it's own EL3 physical timer registers
accessible to secure EL1 in absence of S-EL2. With S-EL2 there is
virtualized view available for EL1 timer registers. So it is
unreasonable for secure world to use non-secure EL1 physical timer
registers. Moreover, the non-secure operating system (Linux in our case)
relies heavily on these EL1 physical timer registers for scheduling
decisions. If NS_TIMER_SWITCH is enabled, it simply breaks the preemption
model of the non-secure world by disabling non-secure timer interrupts
leading to RCU stalls being observed on long running secure world tasks.

The only arch timer register which will benefit from context management
is cntkctl_el1: Counter-timer Kernel Control Register. This enables the
secure and non-secure worlds to independently control accesses to EL0
for counter-timer registers. This is something that OP-TEE uses to
enable ftrace feature for Trusted Applications and SPM_MM uses for EL0
access as well.

Lets enable context management of cntkctl_el1 by default and deprecate
conditional context management of non-secure EL1 physical timer
registers for whom there isn't any upstream user. With that deprecate
this NS_TIMER_SWITCH build option which just adds confusion for the
platform maintainers. It will be eventually dropped following
deprecation policy of TF-A.

Reported-by: Stauffer Thomas MTANA <thomas.stauffer@mt.com>
Reported-by: Andrew Davis <afd@ti.com>
Change-Id: Ifb3a919dc0bf8c05c38895352de5fe94b4f4387e
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

show more ...

Merge "chore(versal2): rename versal2 to Versal Gen 2" into integration

Merge "feat(versal): add support to clear PM specific data" into integration

Merge "fix(versal-net): fix coverity violation prevent buffer overrun" into integration

chore(tc): align core names to Arm Lumex

Adopt core names aligned to Arm Lumex [1]

Nevis => C1-Nano
Gelas => C1-Pro
Travis => C1-Ultra
Alto => C1-Premium

C1-Pro TRM: https://developer.arm.com/docu

chore(tc): align core names to Arm Lumex

Adopt core names aligned to Arm Lumex [1]

Nevis => C1-Nano
Gelas => C1-Pro
Travis => C1-Ultra
Alto => C1-Premium

C1-Pro TRM: https://developer.arm.com/documentation/107771/0102/
C1-Ultra TRM: https://developer.arm.com/documentation/108014/0100/
C1-Premium TRM: https://developer.arm.com/documentation/109416/0100/
C1-Nano TRM: https://developer.arm.com/documentation/107753/0001/

[1]:
https://www.arm.com/product-filter?families=c1%20cpus
https://www.arm.com/products/mobile/compute-subsystems/lumex

Signed-off-by: Min Yao Ng <minyao.ng@arm.com>
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Id4b487ef6a6fd1b00b75b09c5d06d81bce50a15d
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

show more ...

Merge changes from topic "ti-am62lxx-boot-notif" into integration

* changes:
feat(ti): am62lx init: boot notif and version msg
feat(ti): add support for boot notification msg
feat(ti): add mmu

Merge changes from topic "ti-am62lxx-boot-notif" into integration

* changes:
feat(ti): am62lx init: boot notif and version msg
feat(ti): add support for boot notification msg
feat(ti): add mmu regions for am62l soc
feat(ti): build generic timer

show more ...

fix(xilinx): match function type as its declared

This corrects the MISRA violation C2012-8.3:
matching the type of function definition as per its declaration.

Change-Id: Iee582e3bdb3d51fd53938009d2

fix(xilinx): match function type as its declared

This corrects the MISRA violation C2012-8.3:
matching the type of function definition as per its declaration.

Change-Id: Iee582e3bdb3d51fd53938009d29a921569616566
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

show more ...

fix(platforms): typedef operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a

fix(platforms): typedef operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.

Change-Id: I1ed3b7fc1866b34f1086e449ffe648f53c33b008
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

show more ...

fix(platforms): declare unused parameters as void

This corrects the MISRA violation C2012-2.7:
There should be no unused parameters in functions.
Declared unused function parameters as void.

Change

fix(platforms): declare unused parameters as void

This corrects the MISRA violation C2012-2.7:
There should be no unused parameters in functions.
Declared unused function parameters as void.

Change-Id: I8a98d35a4db1494120eaf39bc0f2315deed81664
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

show more ...

fix(platforms): add essential bool type

This corrects the MISRA violation C2012-14.4:
The value 1 does not have an essentially boolean type, it's an integer
constant. Therefore using 'true' from std

fix(platforms): add essential bool type

This corrects the MISRA violation C2012-14.4:
The value 1 does not have an essentially boolean type, it's an integer
constant. Therefore using 'true' from stdbool.h resolves the issue.

Change-Id: If40cb8f583f8eb549dadaa744976741b30ee7d42
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

show more ...

fix(platforms): fix misra violation 10.1

This corrects the MISRA violation C2012-10.1:
Operands shall not be of an inappropriate essential type.
The condition is explicitly checked against boolean v

fix(platforms): fix misra violation 10.1

This corrects the MISRA violation C2012-10.1:
Operands shall not be of an inappropriate essential type.
The condition is explicitly checked against boolean value.
In this scenario, using 'false' rather than '0'resolves the issue.

Change-Id: Icf3d37784181a65d00f6602e8f5e2bf4c65ac9cb
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

show more ...

build(measured-boot)!: move to ext event log lib

Removes in-tree Event Log library implementation and updates all
references to use the external submodule. Updates include paths,
Makefile macros, an

build(measured-boot)!: move to ext event log lib

Removes in-tree Event Log library implementation and updates all
references to use the external submodule. Updates include paths,
Makefile macros, and platform integration logic to link with lib as a
static library.

If you cloned TF-A without the `--recurse-submodules` flag, you can
ensure that this submodule is present by running:

git submodule update --init --recursive

BREAKING-CHANGE: LibEventLog is now included in TF-A as a submodule.
Please run `git submodule update --init --recursive` if you encounter
issues after migrating to the latest version of TF-A.

Change-Id: I723f493033c178759a45ea04118e7cc295dc2438
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

show more ...

refactor(imx8m): simplify RDC console config

imx_rdc_console_access_enable() only updates the RDC configuration for
console UART. Early return was only happening when the correct
configuration was a

refactor(imx8m): simplify RDC console config

imx_rdc_console_access_enable() only updates the RDC configuration for
console UART. Early return was only happening when the correct
configuration was already set.
Return early once the correct entry has been found and updated.

Change-Id: Ic21dd8186b051dd0f51192df68a652ff79d8b8c0
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>

show more ...

fix(imx8m): add RDC entries for all missing UARTs

Commit f7434fa13 ("fix(imx8m): ensure domain permissions for the
console") sets RDC domain to Cortex-A only for console UART. But
this only works if

fix(imx8m): add RDC entries for all missing UARTs

Commit f7434fa13 ("fix(imx8m): ensure domain permissions for the
console") sets RDC domain to Cortex-A only for console UART. But
this only works if there is an RDC configuration entry provided.
Add missing RDC entries using the (reset) default value, so
imx_rdc_console_access_enable() can actually configuration domain
access.

Fixes: f7434fa13507 ("fix(imx8m): ensure domain permissions for the console")
Change-Id: I550dbf2b53795ab43839139c455f2468442a3251
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>

show more ...

Merge "fix(imx8mp): assign wdog1 to domain0 only" into integration

Merge changes from topic "sbsa2" into integration

* changes:
feat(qemu): skip paged image info
feat(optee): check paged image size
feat(qemu-sbsa): support s-el2 and s-el1 spmc