Merge "feat(ast2700): add Aspeed AST2700 platform support" into integration

feat(intel): add intel_rsu_update() to sip_svc_v2

Add smc function id for intel_rsu_update() in sip_svc_v2. For temporarily
saving the RSU application image address before a cold reset is
issued.

S

feat(intel): add intel_rsu_update() to sip_svc_v2

Add smc function id for intel_rsu_update() in sip_svc_v2. For temporarily
saving the RSU application image address before a cold reset is
issued.

Signed-off-by: Mahesh Rao <mahesh.rao@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I43bc7bd5aa5fa9238bceba1d826bf0a34ff87adb

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fix(versal): add missing irq mapping for wakeup src

The commit 0ec6c31320c6 provides irq to device index mapping
which is required to check for IRQs and set peripheral as a
wake source if IRQ is ena

fix(versal): add missing irq mapping for wakeup src

The commit 0ec6c31320c6 provides irq to device index mapping
which is required to check for IRQs and set peripheral as a
wake source if IRQ is enabled. But in that commit some IRQ
numbers are missed. Because of that, wakeup using some
peripheral interrupts will not work. Add those missing IRQ
numbers.

Fixes: 0ec6c31320c6 ("feat(versal): replace irq array with switch case")
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: Icbc773050c328be253702e63e7cf8450c7dee133

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Merge "fix(zynqmp): fix prepare_dtb() memory description" into integration

Merge changes from topic "psci-osi" into integration

* changes:
fix(psci): add optional pwr_domain_validate_suspend to plat_psci_ops_t
fix(sc7280): update pwr_domain_suspend
fix(fvp): update p

Merge changes from topic "psci-osi" into integration

* changes:
fix(psci): add optional pwr_domain_validate_suspend to plat_psci_ops_t
fix(sc7280): update pwr_domain_suspend
fix(fvp): update pwr_domain_suspend

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feat(ast2700): add Aspeed AST2700 platform support

Aspeed AST2700 is a quad-core SoC with ARM Cortex-A35 integrated.
This patch adds the initial platform support for AST2700 and also
updates the doc

feat(ast2700): add Aspeed AST2700 platform support

Aspeed AST2700 is a quad-core SoC with ARM Cortex-A35 integrated.
This patch adds the initial platform support for AST2700 and also
updates the documents.

Change-Id: I1796f7aae5ed2d1799e91fabb8949607959cd9b3
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>

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Merge "chore(xilinx): replace ATF with TFA" into integration

Merge "fix(zynqmp): fix sdei arm_validate_ns_entrypoint()" into integration

fix(zynqmp): fix prepare_dtb() memory description

The commit 8ce2fbffe37d ("fix(zynqmp): fix BLXX memory limits for user
defined values") fixed logic around BL31_LIMIT but didn't update
prepare_dtb(

fix(zynqmp): fix prepare_dtb() memory description

The commit 8ce2fbffe37d ("fix(zynqmp): fix BLXX memory limits for user
defined values") fixed logic around BL31_LIMIT but didn't update
prepare_dtb() which is also using +1 logic.

Change-Id: Ia6de10d992a552ca9cfa39c14261b0f94cda95ec
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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Merge changes from topic "bk/clearups" into integration

* changes:
chore(rme): add make rule for SPD=spmd
chore(bl1): remove redundant bl1_arch_next_el_setup
chore(docs): remove control regist

Merge changes from topic "bk/clearups" into integration

* changes:
chore(rme): add make rule for SPD=spmd
chore(bl1): remove redundant bl1_arch_next_el_setup
chore(docs): remove control register setup section
chore(pauth): remove redundant pauth_disable_el3() call

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fix(zynqmp): fix sdei arm_validate_ns_entrypoint()

Don't use BL31_LIMIT macro for validation logic directly but clearly
mark BL31_LIMIT as 64bit address to avoid compilation error when
-Werror=logic

fix(zynqmp): fix sdei arm_validate_ns_entrypoint()

Don't use BL31_LIMIT macro for validation logic directly but clearly
mark BL31_LIMIT as 64bit address to avoid compilation error when
-Werror=logical-op is passed.

Likely caused by ZYNQMP_ATF_MEM_BASE + ZYNQMP_ATF_MEM_SIZE is in 64bit
logic 0x100000000 and compiler handles it as 32bit value. That's why
error is shown.

Use uint64_t variable for limit and also for base.

Here is command line to replicate this issue:
make realclean; make -j PLAT=zynqmp DEBUG=1 RESET_TO_BL31=1 \
SPD=tspd SDEI_SUPPORT=1 ZYNQMP_ATF_MEM_BASE=0xFFFC0000 \
ZYNQMP_ATF_MEM_SIZE=0x00040000 all -Werror=logical-op

Also error which is coming:
plat/xilinx/zynqmp/zynqmp_sdei.c: In function
'arm_validate_ns_entrypoint':
plat/xilinx/zynqmp/zynqmp_sdei.c:19:40: error: logical 'or' of
collectively exhaustive tests is always true [-Werror=logical-op]
19 | return (entrypoint < BL31_BASE ||
entrypoint > BL31_LIMIT) ? 0 : -1;

Change-Id: Ie1f1b4d2cd94b977aebb72786ecace0b062da418
Signed-off-by: Michal Simek <michal.simek@amd.com>

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Merge changes from topic "st-fixes" into integration

* changes:
fix(spi-nand): add Quad Enable management
fix(st-clock): disabling CKPER clock is not functional on stm32mp13
fix(st-uart): skip

Merge changes from topic "st-fixes" into integration

* changes:
fix(spi-nand): add Quad Enable management
fix(st-clock): disabling CKPER clock is not functional on stm32mp13
fix(st-uart): skip console flush if UART is disabled
fix(st): flush UART at the end of uart_read()
fix(stm32mp1): use the BSEC nodes compatible for stm32mp13
fix(stm32mp13-fdts): correct the BSEC nodes compatible
fix(stm32mp1-fdts): move /omit-if-no-ref/ to overlay files
fix(stm32mp1): properly check PSCI functions return

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Merge "refactor(fvp): nv ctr addr static helper function" into integration

chore(xilinx): replace ATF with TFA

Since the Arm Trusted Firmware(ATF) has been renamed to Trusted
Firmware-A (TF-A), replace all the instances of ATF from code comments,
macros, variables and func

chore(xilinx): replace ATF with TFA

Since the Arm Trusted Firmware(ATF) has been renamed to Trusted
Firmware-A (TF-A), replace all the instances of ATF from code comments,
macros, variables and functions to TF-A.

Change-Id: Iab448d96158612a3effb4e49943f8d6cb43aaad5
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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fix(mediatek): support saving/restoring GICR registers

The GICR_IPRIORITYR[x] registers are not saved or restored in the
original design. When the kernel tries to use them, such as the
pseudo-NMI, i

fix(mediatek): support saving/restoring GICR registers

The GICR_IPRIORITYR[x] registers are not saved or restored in the
original design. When the kernel tries to use them, such as the
pseudo-NMI, it leads crashes and freezes. This patch adds support for
saving/restoring GICR registers.

Change-Id: I9718a75a1410ca14826710dfdf5f3226299fa6e2
Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com>

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Merge changes from topic "version/0.1-gic" into integration

* changes:
feat(qemu-sbsa): handle GIC base
feat(qemu-sbsa): handle platform version

Merge changes I21d65a88,I949cfce9,If4249f22,Id0451bd1,I9e930070, ... into integration

* changes:
feat(mediatek): add APU watchdog timeout control
feat(mt8188): add emi mpu protection for APU sec

Merge changes I21d65a88,I949cfce9,If4249f22,Id0451bd1,I9e930070, ... into integration

* changes:
feat(mediatek): add APU watchdog timeout control
feat(mt8188): add emi mpu protection for APU secure memory
feat(mt8188): add devapc setting of apusys rcx
feat(mt8188): add backup/restore function when power on/off
feat(mediatek): add APU bootup control smc call
feat(mt8188): enable apusys mailbox mpu protect
feat(mt8188): enable apusys domain remap
feat(mt8188): add apusys ao devapc setting
feat(mt8188): increase TZRAM_SIZE from 192KB to 256KB

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feat(mediatek): add APU watchdog timeout control

Add APU watchdog timeout control.

Change-Id: I21d65a88d20b6b2752a75f74487b5fe6596ebdf7
Signed-off-by: Chungying Lu <chungying.lu@mediatek.com>
Signe

feat(mediatek): add APU watchdog timeout control

Add APU watchdog timeout control.

Change-Id: I21d65a88d20b6b2752a75f74487b5fe6596ebdf7
Signed-off-by: Chungying Lu <chungying.lu@mediatek.com>
Signed-off-by: Karl Li <karl.li@mediatek.com>

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feat(mt8188): add emi mpu protection for APU secure memory

Add emi mpu protection of APU secure memory.

Change-Id: I949cfce97565d8a313caae4ea41af60a171042a6
Signed-off-by: Chungying Lu <chungying.l

feat(mt8188): add emi mpu protection for APU secure memory

Add emi mpu protection of APU secure memory.

Change-Id: I949cfce97565d8a313caae4ea41af60a171042a6
Signed-off-by: Chungying Lu <chungying.lu@mediatek.com>
Signed-off-by: Karl Li <karl.li@mediatek.com>

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feat(mt8188): add devapc setting of apusys rcx

Apusys rcx is a subsys in apusys, and it is a basic domain of APU and
it connects several components in APU.
The devapc control of apusys rcx is also i

feat(mt8188): add devapc setting of apusys rcx

Apusys rcx is a subsys in apusys, and it is a basic domain of APU and
it connects several components in APU.
The devapc control of apusys rcx is also inside APU and it can only be
set when APU is powered on.
Then apusys kernel driver will trigger rcx devapc init by ATF smc call.

Change-Id: If4249f22a08690b1e4f5aa5f0cbfb54ccacf90e1
Signed-off-by: Karl Li <karl.li@mediatek.com>
Signed-off-by: Chungying Lu <chungying.lu@mediatek.com>

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feat(mt8188): add backup/restore function when power on/off

Add APU backup/restore function when power on/off.

Change-Id: Id0451bd12f402e1acabeb5c12266a2e01836e9dd
Signed-off-by: Chungying Lu <chun

feat(mt8188): add backup/restore function when power on/off

Add APU backup/restore function when power on/off.

Change-Id: Id0451bd12f402e1acabeb5c12266a2e01836e9dd
Signed-off-by: Chungying Lu <chungying.lu@mediatek.com>
Signed-off-by: Karl Li <karl.li@mediatek.com>

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feat(mediatek): add APU bootup control smc call

Add APU bootup control smc call.
The steps of bootup flow:
1. set up APU config.
2. reset APU.
3. set up APU boot config.
4. boot APU.

Change

feat(mediatek): add APU bootup control smc call

Add APU bootup control smc call.
The steps of bootup flow:
1. set up APU config.
2. reset APU.
3. set up APU boot config.
4. boot APU.

Change-Id: I9e930070a64c7c4dcaa3a8b3d28b897823e9f53c
Signed-off-by: Chungying Lu <chungying.lu@mediatek.com>
Signed-off-by: Karl Li <karl.li@mediatek.com>

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feat(mt8188): enable apusys mailbox mpu protect

Enable apusys mailbox mpu protect.

Change-Id: Idbf67084037b7ecf4926f57a901075f98540ee57
Signed-off-by: Karl Li <karl.li@mediatek.com>
Signed-off-by:

feat(mt8188): enable apusys mailbox mpu protect

Enable apusys mailbox mpu protect.

Change-Id: Idbf67084037b7ecf4926f57a901075f98540ee57
Signed-off-by: Karl Li <karl.li@mediatek.com>
Signed-off-by: Chungying Lu <chungying.lu@mediatek.com>

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feat(mt8188): enable apusys domain remap

Enable apusys domain remap to protect no-protect memory.
- Remap request which from domain 5 to domain 14.
- Remap request which from domain 7 to domain

feat(mt8188): enable apusys domain remap

Enable apusys domain remap to protect no-protect memory.
- Remap request which from domain 5 to domain 14.
- Remap request which from domain 7 to domain 14.

Change-Id: Iccd188e3b8edbe916fa9767c841a844b66c6011f
Signed-off-by: Karl Li <karl.li@mediatek.com>
Signed-off-by: Chungying Lu <chungying.lu@mediatek.com>

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feat(mt8188): add apusys ao devapc setting

Apusys ao devapc is a set of control registers inside APU, and it
controls the access permission of APU ao domain.
Moreover, apusys ao devapc must be set a

feat(mt8188): add apusys ao devapc setting

Apusys ao devapc is a set of control registers inside APU, and it
controls the access permission of APU ao domain.
Moreover, apusys ao devapc must be set after apusys power init, so
we need to place the drivers in TF-A instead of coreboot.

Change-Id: Ife849c32d4dd9dca15432d4b8a51753fde61b148
Signed-off-by: Karl Li <karl.li@mediatek.com>
Signed-off-by: Chungying Lu <chungying.lu@mediatek.com>

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