History log of /rk3399_ARM-atf/plat/ (Results 2601 – 2625 of 8950)
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02df499017-May-2023 Jit Loon Lim <jit.loon.lim@intel.com>

feat(intel): ccu driver for Agilex5 SoC FPGA

This patch is used to implement CCU driver for
Agilex5 SoC FPGA.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Ic5e38499c969486682761c

feat(intel): ccu driver for Agilex5 SoC FPGA

This patch is used to implement CCU driver for
Agilex5 SoC FPGA.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Ic5e38499c969486682761c00d9e050e60c883725

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intel/soc/common/drivers/ccu/ncore_ccu.c
intel/soc/common/drivers/ccu/ncore_ccu.h
4754925017-May-2023 Jit Loon Lim <jit.loon.lim@intel.com>

feat(intel): vab support for Agilex5 SoC FPGA

This patch is used to implement VAB to support for
Agilex5 SoC FPGA.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I421f11225cd549f35

feat(intel): vab support for Agilex5 SoC FPGA

This patch is used to implement VAB to support for
Agilex5 SoC FPGA.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I421f11225cd549f35f06e87b8ad2c44b716b2a78

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intel/soc/common/include/socfpga_vab.h
intel/soc/common/socfpga_vab.c
ddaf02d117-May-2023 Jit Loon Lim <jit.loon.lim@intel.com>

feat(intel): sdmmc/nand/combo-phy/qspi driver for Agilex5 SoC FPGA

This patch is used to implement sdmmc/nand/combo-phy
driver to support Cadence IP for Agilex5 SoC FPGA.
1. Added SDMMC/NAND/COMBO-

feat(intel): sdmmc/nand/combo-phy/qspi driver for Agilex5 SoC FPGA

This patch is used to implement sdmmc/nand/combo-phy
driver to support Cadence IP for Agilex5 SoC FPGA.
1. Added SDMMC/NAND/COMBO-PHY support.
2. Updated product name -> Agilex5
3. Updated QSPI base address

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I6db689d2b784c9f59a25701ab34517f6f6b0a0e6

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/rk3399_ARM-atf/drivers/cadence/combo_phy/cdns_combo_phy.c
/rk3399_ARM-atf/drivers/cadence/emmc/cdns_sdmmc.c
/rk3399_ARM-atf/drivers/cadence/nand/cdns_nand.c
/rk3399_ARM-atf/include/drivers/cadence/cdns_combo_phy.h
/rk3399_ARM-atf/include/drivers/cadence/cdns_nand.h
/rk3399_ARM-atf/include/drivers/cadence/cdns_sdmmc.h
intel/soc/common/drivers/combophy/combophy.c
intel/soc/common/drivers/combophy/combophy.h
intel/soc/common/drivers/nand/nand.c
intel/soc/common/drivers/nand/nand.h
intel/soc/common/drivers/qspi/cadence_qspi.c
intel/soc/common/drivers/qspi/cadence_qspi.h
intel/soc/common/drivers/sdmmc/sdmmc.c
intel/soc/common/drivers/sdmmc/sdmmc.h
intel/soc/common/socfpga_storage.c
29461e4c17-May-2023 Jit Loon Lim <jit.loon.lim@intel.com>

feat(intel): ddr driver for Agilex5 SoC FPGA

This patch is used to implement ddr driver to
support IO96b for Agilex5 SoC FPGA.
1. Added DDR support.
2. Updated product name -> Agilex5

Signed-off-

feat(intel): ddr driver for Agilex5 SoC FPGA

This patch is used to implement ddr driver to
support IO96b for Agilex5 SoC FPGA.
1. Added DDR support.
2. Updated product name -> Agilex5

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Ibda053de6dbec4a0f12f011d8feeb6c5890fc7a4

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intel/soc/common/drivers/ddr/ddr.c
intel/soc/common/drivers/ddr/ddr.h
a8bf898f17-May-2023 Jit Loon Lim <jit.loon.lim@intel.com>

feat(intel): power manager for Agilex5 SoC FPGA

This patch is used to implement power manager data
support for Agilex5 SoC FPGA.
1. Added power manager support.
2. Updated product name -> Agilex5

feat(intel): power manager for Agilex5 SoC FPGA

This patch is used to implement power manager data
support for Agilex5 SoC FPGA.
1. Added power manager support.
2. Updated product name -> Agilex5

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: If0630c5088a1bc63dff64b1aab225fc70effa6e3

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intel/soc/agilex5/include/agilex5_power_manager.h
intel/soc/agilex5/soc/agilex5_power_manager.c
79626f4617-May-2023 Jit Loon Lim <jit.loon.lim@intel.com>

feat(intel): cold/warm reset and smp support for Agilex5 SoC FPGA

This patch is used to implement
1. Cold/Warm reset and SMP support for
Agilex5 SoC FPGA
2. Updated product name -> Agilex5

Signe

feat(intel): cold/warm reset and smp support for Agilex5 SoC FPGA

This patch is used to implement
1. Cold/Warm reset and SMP support for
Agilex5 SoC FPGA
2. Updated product name -> Agilex5

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I2c0645bcbf3a5907a4c79f35cffe674920b48f9d

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intel/soc/common/socfpga_psci.c
intel/soc/common/socfpga_storage.c
intel/soc/common/socfpga_topology.c
9b8d813c17-May-2023 Jit Loon Lim <jit.loon.lim@intel.com>

feat(intel): reset manager support for Agilex5 SoC FPGA

This patch is used to enable reset manager support
for Agilex5 SoC FPGA.
1. Added HPS bridges support
a. SOC2FPGA
b. LWSOC2FPGA
c. F2SD

feat(intel): reset manager support for Agilex5 SoC FPGA

This patch is used to enable reset manager support
for Agilex5 SoC FPGA.
1. Added HPS bridges support
a. SOC2FPGA
b. LWSOC2FPGA
c. F2SDRAM
d. F2SOC
2. Added EMULATOR support
3. Added WDT support
4. Updated product name -> Agilex5
5. Added SMP support

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Icab15b25f787fdccce1de75d102604db23beaf11

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intel/soc/common/include/socfpga_f2sdram_manager.h
intel/soc/common/include/socfpga_reset_manager.h
intel/soc/common/soc/socfpga_reset_manager.c
8e59b9f417-May-2023 Jit Loon Lim <jit.loon.lim@intel.com>

feat(intel): mailbox and SMC support for Agilex5 SoC FPGA

This patch is used to enable mailbox and SMC support
for Agilex5 SoC FPGA.
1. Enabled mailbox and SMC support.
2. Updated product name ->

feat(intel): mailbox and SMC support for Agilex5 SoC FPGA

This patch is used to enable mailbox and SMC support
for Agilex5 SoC FPGA.
1. Enabled mailbox and SMC support.
2. Updated product name -> Agilex5
3. Updated register address based on y22ww52.2 RTL
4. Updated TSN register base address

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I152bee5668b96ef599ded09945167f27a71f23fe

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intel/soc/common/include/socfpga_mailbox.h
intel/soc/common/soc/socfpga_emac.c
intel/soc/common/soc/socfpga_mailbox.c
intel/soc/common/socfpga_sip_svc.c
7618403117-May-2023 Jit Loon Lim <jit.loon.lim@intel.com>

feat(intel): system manager support for Agilex5 SoC FPGA

This patch is used to implement system manager data
support for Agilex5 SoC FPGA.

1. Initial SM bring up
2. Support Candence SDMMC/NAND/CO

feat(intel): system manager support for Agilex5 SoC FPGA

This patch is used to implement system manager data
support for Agilex5 SoC FPGA.

1. Initial SM bring up
2. Support Candence SDMMC/NAND/COMBO PHY
3. Updated product name -> Agilex5
4. Updated register address based on y22ww52.2 RTL

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I12712bddfb67e36a2bf56d2d98ea4ca3037f0a82

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intel/soc/agilex5/include/agilex5_system_manager.h
intel/soc/common/include/socfpga_system_manager.h
18adb4ef17-May-2023 Jit Loon Lim <jit.loon.lim@intel.com>

feat(intel): memory controller support for Agilex5 SoC FPGA

This patch is used to enable memory controller support
for Agilex5 SoC FPGA.
1. Added memory controller support.
2. Updated product name

feat(intel): memory controller support for Agilex5 SoC FPGA

This patch is used to enable memory controller support
for Agilex5 SoC FPGA.
1. Added memory controller support.
2. Updated product name -> Agilex5

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I8381b82eeed939b970a7410a6181a514f2c90caa

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intel/soc/agilex5/include/agilex5_memory_controller.h
intel/soc/agilex5/soc/agilex5_memory_controller.c
1b1a3eb117-May-2023 Jit Loon Lim <jit.loon.lim@intel.com>

feat(intel): clock manager support for Agilex5 SoC FPGA

This patch is used to enable clock manager support
for Agilex5 SoC FPGA.
1. Added clock manager support.
2. Updated product name -> Agilex5

feat(intel): clock manager support for Agilex5 SoC FPGA

This patch is used to enable clock manager support
for Agilex5 SoC FPGA.
1. Added clock manager support.
2. Updated product name -> Agilex5
3. Updated register address based on y22ww52.2 RTL
4. Standardized handoff handler.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Ic4c57a1955136ef7d22253c3ca52226e5620751b

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intel/soc/agilex5/include/agilex5_clock_manager.h
intel/soc/agilex5/soc/agilex5_clock_manager.c
4a577da617-May-2023 Jit Loon Lim <jit.loon.lim@intel.com>

feat(intel): mmc support for Agilex5 SoC FPGA

This patch is used to enable MMC support for
Agilex5 SoC FPGA.
1. Added MMC support.
2. Updated product name -> Agilex5
3. Updated register address b

feat(intel): mmc support for Agilex5 SoC FPGA

This patch is used to enable MMC support for
Agilex5 SoC FPGA.
1. Added MMC support.
2. Updated product name -> Agilex5
3. Updated register address based on y22ww52.2 RTL

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I47f5c7f063fc443f29c2af612121abe672ed422b

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intel/soc/agilex5/include/agilex5_mmc.h
intel/soc/agilex5/soc/agilex5_mmc.c
34971f8117-May-2023 Jit Loon Lim <jit.loon.lim@intel.com>

feat(intel): uart support for Agilex5 SoC FPGA

This patch is used to enable UART & WDT support
for Agilex5 SoC FPGA.

1. Added watchdog support.
2. Updated product name -> Agilex5

Signed-off-by:

feat(intel): uart support for Agilex5 SoC FPGA

This patch is used to enable UART & WDT support
for Agilex5 SoC FPGA.

1. Added watchdog support.
2. Updated product name -> Agilex5

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I9346cfde6e033026e4c1e612250e9521bc6b0d47

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intel/soc/common/drivers/wdt/watchdog.h
fcbb5cf717-May-2023 Jit Loon Lim <jit.loon.lim@intel.com>

feat(intel): pinmux, peripheral and Handoff support for Agilex5 SoC FPGA

This patch is used to enable pinmux, peripheral and handoff support
for Agilex5 SoC FPGA.
1. Initial handoff bring up
2. Ad

feat(intel): pinmux, peripheral and Handoff support for Agilex5 SoC FPGA

This patch is used to enable pinmux, peripheral and handoff support
for Agilex5 SoC FPGA.
1. Initial handoff bring up
2. Added power manager handoff implementation
3. Added sdram handoff implementation
4. Updated product name -> Agilex5
5. Updated register address based on y22ww52.2 RTL

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I4b0176bc86c57823127bf41086306015d702577d

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intel/soc/agilex5/include/agilex5_pinmux.h
intel/soc/agilex5/soc/agilex5_pinmux.c
intel/soc/common/include/socfpga_handoff.h
intel/soc/common/soc/socfpga_handoff.c
e7644eb604-Jul-2023 Manish Pandey <manish.pandey2@arm.com>

Merge "chore(xilinx): reorder include files as per TF-A guidelines" into integration


xilinx/common/include/pm_ipi.h
xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c
xilinx/common/pm_service/pm_ipi.c
xilinx/common/pm_service/pm_svc_main.c
xilinx/versal/aarch64/versal_helpers.S
xilinx/versal/bl31_versal_setup.c
xilinx/versal/include/plat_ipi.h
xilinx/versal/include/plat_pm_common.h
xilinx/versal/include/plat_private.h
xilinx/versal/plat_psci.c
xilinx/versal/plat_versal.c
xilinx/versal/pm_service/pm_client.c
xilinx/versal/versal_gicv3.c
xilinx/versal/versal_ipi.c
xilinx/versal_net/aarch64/versal_net_helpers.S
xilinx/versal_net/pm_service/pm_client.c
xilinx/zynqmp/aarch64/zynqmp_common.c
xilinx/zynqmp/bl31_zynqmp_setup.c
xilinx/zynqmp/plat_zynqmp.c
xilinx/zynqmp/pm_service/pm_api_ioctl.c
xilinx/zynqmp/pm_service/pm_client.c
xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.c
xilinx/zynqmp/tsp/tsp_plat_setup.c
xilinx/zynqmp/zynqmp_ehf.c
xilinx/zynqmp/zynqmp_sdei.c
38a0548504-Jul-2023 Manish Pandey <manish.pandey2@arm.com>

Merge "fix(versal-net): correct device node indexes" into integration


/rk3399_ARM-atf/drivers/st/uart/aarch32/stm32_console.S
xilinx/common/include/pm_node.h
106aa54d09-Jun-2023 Jit Loon Lim <jit.loon.lim@intel.com>

fix(intel): fix ncore ccu snoop dvm enable bug

Incorrect value stored in Coherent Subsystem ACE DVM Snoop Enable
register (CSADSER0). Set individual bit othervise previous value
is overwritten.

Sig

fix(intel): fix ncore ccu snoop dvm enable bug

Incorrect value stored in Coherent Subsystem ACE DVM Snoop Enable
register (CSADSER0). Set individual bit othervise previous value
is overwritten.

Signed-off-by: Anders Hedlund <anders.hedlund@windriver.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Ib72fed261cbc3076ce385e19c4a5fa8e9e8b9924

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intel/soc/common/drivers/ccu/ncore_ccu.c
7b0c95ab25-May-2023 Werner Lewis <werner.lewis@arm.com>

fix(n1sdp): configure platform specific secure SPIs

Previous implementation used common CSS interrupts, which do not match
the N1SDP platform interrupt map. Updated to configure Secure
interrupts ac

fix(n1sdp): configure platform specific secure SPIs

Previous implementation used common CSS interrupts, which do not match
the N1SDP platform interrupt map. Updated to configure Secure
interrupts according to the N1SDP TRM and InfraSYSDESIGN4.0
specification. Additionally, unused definitions from legacy interrupt
configuration are removed.

Signed-off-by: Werner Lewis <werner.lewis@arm.com>
Change-Id: I3dd4bcd4875e138057c62d937572d446b8f88471

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arm/board/n1sdp/include/platform_def.h
214de62c04-Jul-2023 Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

feat(qemu): add "neoverse-v1" cpu support

Add support to qemu "neoverse-v1" cpu for "qemu_sbsa" ('sbsa-ref')
platform.

Change-Id: Id710e2b960e7938d2dbe7a88d9e158a7009fc3d1
Signed-off-by: Marcin Jus

feat(qemu): add "neoverse-v1" cpu support

Add support to qemu "neoverse-v1" cpu for "qemu_sbsa" ('sbsa-ref')
platform.

Change-Id: Id710e2b960e7938d2dbe7a88d9e158a7009fc3d1
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

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qemu/qemu_sbsa/platform.mk
cd89a70416-Jun-2023 Manish V Badarkhe <Manish.Badarkhe@arm.com>

refactor(tc): update RSS driver inteface calls

In order to comply with the previous RSS driver change,
interface calls have been updated.

Change-Id: I645f6e8638cedfa6ff92d07b93cbaf38bdb2e09f
Signed

refactor(tc): update RSS driver inteface calls

In order to comply with the previous RSS driver change,
interface calls have been updated.

Change-Id: I645f6e8638cedfa6ff92d07b93cbaf38bdb2e09f
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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arm/board/tc/tc_bl1_measured_boot.c
arm/board/tc/tc_bl2_measured_boot.c
arm/board/tc/tc_common_measured_boot.c
a99a378d16-Jun-2023 Manish V Badarkhe <Manish.Badarkhe@arm.com>

refactor(fvp): update RSS driver inteface calls

In order to comply with the previous RSS driver change,
interface calls have been updated.

Change-Id: I0a1f3c6a6f8017468d86903cc0158805c6461c28
Signe

refactor(fvp): update RSS driver inteface calls

In order to comply with the previous RSS driver change,
interface calls have been updated.

Change-Id: I0a1f3c6a6f8017468d86903cc0158805c6461c28
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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/rk3399_ARM-atf/drivers/measured_boot/rss/rss_measured_boot.c
/rk3399_ARM-atf/include/drivers/measured_boot/rss/rss_measured_boot.h
arm/board/fvp/fvp_bl1_measured_boot.c
arm/board/fvp/fvp_bl2_measured_boot.c
arm/board/fvp/fvp_common_measured_boot.c
8e31faa030-Jun-2023 Joanna Farley <joanna.farley@arm.com>

Merge changes from topic "xlnx_handoff_changes" into integration

* changes:
chore(xilinx): update warning message
feat(versal-net): add cluster check in handoff parameters
feat(versal-net): ge

Merge changes from topic "xlnx_handoff_changes" into integration

* changes:
chore(xilinx): update warning message
feat(versal-net): add cluster check in handoff parameters
feat(versal-net): get the handoff params using IPI
chore(xilinx): replace fsbl with xbl

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xilinx/common/include/plat_startup.h
xilinx/common/plat_startup.c
xilinx/versal/bl31_versal_setup.c
xilinx/versal_net/bl31_versal_net_setup.c
xilinx/zynqmp/bl31_zynqmp_setup.c
66b5620c28-Jun-2023 Jay Buddhabhatti <jay.buddhabhatti@amd.com>

fix(versal-net): correct device node indexes

Currently, the peripheral node indexes are incorrect
for Versal NET due to which incorrect node error is
generated and permission to set the device as wa

fix(versal-net): correct device node indexes

Currently, the peripheral node indexes are incorrect
for Versal NET due to which incorrect node error is
generated and permission to set the device as wakeup
source is failed. Correct Versal NET peripheral node
indexes to fix above issue.

Fixes: 662aafd6475e ("feat(xilinx): add device node indexes")
Change-Id: I4a2d76f375645e13512599a0272d9322ff6fafd3
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>

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xilinx/common/include/pm_node.h
1c62cc7f30-Jun-2023 Manish Pandey <manish.pandey2@arm.com>

Merge "fix(mediatek): support saving/restoring GICR registers" into integration


mediatek/drivers/gic600/mt_gic_v3.c
a0a4d86c22-Jun-2023 Akshay Belsare <akshay.belsare@amd.com>

chore(xilinx): update warning message

Update the Warning message to be more informative
about the warning being printed.

Change-Id: I923dc5dd760908844d5e1ac8542fd1b04c9f0af5
Signed-off-by: Akshay B

chore(xilinx): update warning message

Update the Warning message to be more informative
about the warning being printed.

Change-Id: I923dc5dd760908844d5e1ac8542fd1b04c9f0af5
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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xilinx/common/plat_startup.c

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