fix(plat/sgi): update PLAT_SP_PRI macro definition

PLAT_SP_PRI EHF priority is defined to be same as the PLAT_RAS_PRI EHF
priority. But PLAT_RAS_PRIORITY is defined only if RAS_FFH_SUPPORT is
enable

fix(plat/sgi): update PLAT_SP_PRI macro definition

PLAT_SP_PRI EHF priority is defined to be same as the PLAT_RAS_PRI EHF
priority. But PLAT_RAS_PRIORITY is defined only if RAS_FFH_SUPPORT is
enabled. This patch defines priority value for PLAT_SP_PRI if
RAS_FFH_SUPPORT is not enabled.

Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
Change-Id: Ib3747317d2ecc088fbbf1f5f283726a330454c93

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chore(xilinx): follow kernel doc format for functional documentation

For TF-A, there is no format specified for functional documentation.
For AMD-Xilinx platforms, following kernel-doc format for th

chore(xilinx): follow kernel doc format for functional documentation

For TF-A, there is no format specified for functional documentation.
For AMD-Xilinx platforms, following kernel-doc format for the functional
documentation to make sure AMD-xilinx documentation is align with
actual code.

For example use kernel-doc from linux to call:
<linux>/scripts/kernel-doc -man -v 1 >/dev/null file...

Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: Idcc9def408b6c8da35b36f67ef82fc00890e998c

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refactor(build): merge march32/64 directives

Both march32-directive and march64-directive eventually generate the
same march option that will passed to compiler.

Merge this two separate directives

refactor(build): merge march32/64 directives

Both march32-directive and march64-directive eventually generate the
same march option that will passed to compiler.

Merge this two separate directives to a common one as march-directive.

Change-Id: I220d2b782eb3b54e13ffd5b6a581d0e6da68756a
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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fix(morello): configure platform specific secure SPIs

Previous implementation used common CSS interrupts, which do not match
the Morello platform interrupt map. Updated to configure Secure
interrupt

fix(morello): configure platform specific secure SPIs

Previous implementation used common CSS interrupts, which do not match
the Morello platform interrupt map. Updated to configure Secure
interrupts according to the Morello TRM and InfraSYSDESIGN4.0
specification.

Signed-off-by: Werner Lewis <werner.lewis@arm.com>
Change-Id: I783a472d92601d86f1844f0d035dd0d036b2bfca

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Merge changes from topic "msm8916-spmin" into integration

* changes:
docs(msm8916): document new build options
feat(msm8916): allow selecting which UART to use
feat(msm8916): add SP_MIN port f

Merge changes from topic "msm8916-spmin" into integration

* changes:
docs(msm8916): document new build options
feat(msm8916): allow selecting which UART to use
feat(msm8916): add SP_MIN port for AArch32
refactor(msm8916): detect cold boot in plat_get_my_entrypoint
feat(msm8916): add Test Secure Payload (TSP) port
build(msm8916): place bl32 directly after bl31
refactor(msm8916): separate common platform setup code

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Merge changes from topic "ffa_el3_spmc_fixes" into integration

* changes:
fix(tsp): fix destination ID in direct request
fix(el3-spm): fix LSP direct message response
fix(el3-spm): improve dir

Merge changes from topic "ffa_el3_spmc_fixes" into integration

* changes:
fix(tsp): fix destination ID in direct request
fix(el3-spm): fix LSP direct message response
fix(el3-spm): improve direct messaging validation

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feat(stm32mp1): add FWU with boot from NOR-SPI

Refactor the SDCARD/EMMC FWU, to add the NOR-SPI use case.
SPI-NOR FWU won't use a real partition uuid to find the correct FIP,
but the UUID from metad

feat(stm32mp1): add FWU with boot from NOR-SPI

Refactor the SDCARD/EMMC FWU, to add the NOR-SPI use case.
SPI-NOR FWU won't use a real partition uuid to find the correct FIP,
but the UUID from metadata will correspond with a hardcoded offset in
the NOR.
While at it change some __unused keywords to __maybe_unused to ease
checkpatch.pl analysis.

Signed-off-by: Frank Bodammer <frank.bodammer@siemens.com>
Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@foss.st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I2fe56ba8534a3c5dfaf8aeb16e7b286909883cc2

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Merge "feat(plat/qemu): add sdei support for QEMU" into integration

fix(el3-spm): fix LSP direct message response

Ensure that the example LSP correctly sets the
sender/receiver field in a direct response.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id

fix(el3-spm): fix LSP direct message response

Ensure that the example LSP correctly sets the
sender/receiver field in a direct response.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I482c08d4657617adb00b0f3cf3c8ddc84f1bf7c8

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feat(fvp): allow configurable FVP Trusted SRAM size

In some build configurations TF-A can exceed the existing 256KB SRAM,
triggering a build failure. More recent versions of the base FVP allow
you t

feat(fvp): allow configurable FVP Trusted SRAM size

In some build configurations TF-A can exceed the existing 256KB SRAM,
triggering a build failure. More recent versions of the base FVP allow
you to configure a larger Trusted SRAM of 512KB.

This change introduces the `FVP_TRUSTED_SRAM_SIZE` build option, which
allows you to explicitly specify how much of the Trusted SRAM to
utilise, e.g.:

FVP_TRUSTED_SRAM_SIZE=384

This allows previously-failing configurations to build successfully by
utilising more than the originally-allocated 256KB of the Trusted SRAM
while maintaining compatibility with older configurations/models that
only require/have 256KB.

Change-Id: I8344d3718564cd2bd53f1e6860e2fe341ae240b0
Signed-off-by: Chris Kay <chris.kay@arm.com>

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feat(msm8916): allow selecting which UART to use

At the moment the msm8916 platform port always uses UART number 2 for
debug output. In some situations it is necessary to change this, either
because

feat(msm8916): allow selecting which UART to use

At the moment the msm8916 platform port always uses UART number 2 for
debug output. In some situations it is necessary to change this, either
because only the other UART is exposed on the board or for runtime
debugging, to avoid conflicting with the normal world.

Make the UART to use configurable using QTI_UART_NUM on the make
command line and also add QTI_RUNTIME_UART as an option to keep using
the UART after early boot. The latter is disabled by default since it
requires reserving the UART and related clocks inside the normal world.

Change-Id: I14725f954bbcecebcf317e8601922a3d00f2ec28
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

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feat(msm8916): add SP_MIN port for AArch32

Use the new shared msm8916 setup code to allow compiling the minimal
AArch32 Secure Payload (SP_MIN) as simple PSCI implementation.

AArch64 is preferred f

feat(msm8916): add SP_MIN port for AArch32

Use the new shared msm8916 setup code to allow compiling the minimal
AArch32 Secure Payload (SP_MIN) as simple PSCI implementation.

AArch64 is preferred for the Cortex-A53 cores in MSM8916 but there are
some similar platforms with AArch32-only Cortex-A7 cores that can
benefit from this in future changes.

The AArch32 assembly implementation for msm8916_helpers.S and
uartdm_console.S is a direct port of the AArch64 implementation.
Only plat_get_my_entrypoint is slightly different because there is no
need to handle the "boot remapper" on cold boot for AArch32.

Change-Id: Idf160e86fb3e685fcedec3e051400e6273997b74
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

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refactor(msm8916): detect cold boot in plat_get_my_entrypoint

The msm8916 platform port needs to disable the TCM redirect to the L2
cache as early as possible during cold boot to avoid crashes. Righ

refactor(msm8916): detect cold boot in plat_get_my_entrypoint

The msm8916 platform port needs to disable the TCM redirect to the L2
cache as early as possible during cold boot to avoid crashes. Right now
this is done in plat_reset_handler by checking if BL31 was started
through the "boot remapper", which redirects memory accesses around the
fixed CPU reset address (0x0) to the actual link address of BL31. On
AArch64 this is always the case during cold boot, since a CPU reset was
necessary to switch from AArch32 in the initial bootloader to AArch64.

On AArch32, SP_MIN starts running at the real link address immediately,
so the initial cold boot must be detected with a different approach.

To keep the AArch32 and AArch64 implementation of this functionality
consistent, move this functionality to plat_get_my_entrypoint, by
checking if the msm8916_entry_point is still zero or was already
updated for later warm boots by the PSCI code.

Also, avoid entering BL31 twice and instead add the BL31_BASE offset
to the return address in the link register. This allows preserving the
bootloader arguments in x0-x3 because they otherwise get lost.

Change-Id: I90286c6cacf23f44ed7930a3e7e33804ca63c391
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

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feat(msm8916): add Test Secure Payload (TSP) port

Use the new shared msm8916 setup code to easily allow compiling the
Test Secure Payload (TSP) for the msm8916 platform.

Unlike BL31, TSP only calls

feat(msm8916): add Test Secure Payload (TSP) port

Use the new shared msm8916 setup code to easily allow compiling the
Test Secure Payload (TSP) for the msm8916 platform.

Unlike BL31, TSP only calls msm8916_platform_setup() but not
msm8916_configure() because this is already done in BL31.

Change-Id: I3225ef9e61387d49870e9759ffd5b899a8805961
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

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build(msm8916): place bl32 directly after bl31

At the moment there are two entirely separate memory regions for BL31
and BL32. However, since BL31 is very small (<= 128 KiB) there is
actually still

build(msm8916): place bl32 directly after bl31

At the moment there are two entirely separate memory regions for BL31
and BL32. However, since BL31 is very small (<= 128 KiB) there is
actually still plenty of space after BL31.

Drop the extra memory region for BL32 and place it directly after BL31
(i.e. BL31_LIMIT). If needed it is still possible to change it on the
make command line.

While at it, move the definitions to the bottom of the make file so
they come immediately before the related add_define calls.

Change-Id: I5184dcc2d89a92f1384508f973d56fd963e7befb
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

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refactor(msm8916): separate common platform setup code

In preparation of adding BL32 support for the msm8916 platform
(AArch32/SP_MIN and TSP), separate the common platform setup code into
shared ms

refactor(msm8916): separate common platform setup code

In preparation of adding BL32 support for the msm8916 platform
(AArch32/SP_MIN and TSP), separate the common platform setup code into
shared msm8916_setup.c and msm8916_config.c files which can be called
from both BL31 and BL32.

msm8916_setup.c contains the relevant shared code for BL31/SP_MIN/TSP,
while msm8916_config.c is cold boot configuration code that is only
relevant for BL31 and SP_MIN (but not TSP).

No functional change.

Change-Id: I055522d5ad8c03dfb8e09236dc47dd383a480e95
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

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Merge changes from topic "xlnx_zynqmp_sizefixes" into integration

* changes:
fix(zynqmp): type cast addresses to fix overflow issue
fix: integer suffix macro definition

Merge "fix(build): include Cortex-A78AE cpu file for FVP" into integration

Merge "feat(intel): add intel_rsu_update() to sip_svc_v2" into integration

fix(zynqmp): type cast addresses to fix overflow issue

Type cast the build time base and size argument to unsigned integer
and the limit derived from these two as unsigned long to avoid
size overflo

fix(zynqmp): type cast addresses to fix overflow issue

Type cast the build time base and size argument to unsigned integer
and the limit derived from these two as unsigned long to avoid
size overflow issue during build.

For zynqmp platform, calculating the limit without typecasting results
in build error as follows

make -j DEBUG=0 RESET_TO_BL31=1 PLAT=zynqmp \
ZYNQMP_ATF_MEM_BASE=0x70000000 ZYNQMP_ATF_MEM_SIZE=0x10000000 \
XILINX_OF_BOARD_DTB_ADDR=0x100000 bl31

plat/xilinx/zynqmp/include/platform_def.h:51:62:
error: integer overflow in expression of type 'int' results
in '-2147483648' [-Werror=overflow]
51 | # define BL31_LIMIT (ZYNQMP_ATF_MEM_BASE + ZYNQMP_ATF_MEM_SIZE)

Change-Id: Id093a50e748884d4fba65626e94f361f6c23cecc
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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Merge changes I814cdadb,I429eb473,I441f9a60 into integration

* changes:
fix(n1sdp): fix spi_ids range for n1sdp multichip boot
fix(gicv3): move invocation of gicv3_get_multichip_base function

Merge changes I814cdadb,I429eb473,I441f9a60 into integration

* changes:
fix(n1sdp): fix spi_ids range for n1sdp multichip boot
fix(gicv3): move invocation of gicv3_get_multichip_base function
fix(gic600): fix gic600 maximum SPI ID

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fix(n1sdp): fix spi_ids range for n1sdp multichip boot

According to GIC-600 TRM, it supports upto 960 SPIs.
This patch configures the SPI IDs range to 32-991, and distributes
them equally across bot

fix(n1sdp): fix spi_ids range for n1sdp multichip boot

According to GIC-600 TRM, it supports upto 960 SPIs.
This patch configures the SPI IDs range to 32-991, and distributes
them equally across both the chips.

Signed-off-by: sahil <sahil@arm.com>
Change-Id: I814cdadb59c8765c239ae0375e547718b7f208ff

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feat(plat/qemu): add sdei support for QEMU

Add sdei support for QEMU, this is to let jailhouse Hypervisor
use SDEI to do hypervisor management, after physical IRQ
has been disabled routing.

Note: T

feat(plat/qemu): add sdei support for QEMU

Add sdei support for QEMU, this is to let jailhouse Hypervisor
use SDEI to do hypervisor management, after physical IRQ
has been disabled routing.

Note: To enable SDEI in QEMU, it needs to set "SDEI_SUPPORT=1
EL3_EXCEPTION_HANDLING=1" when compiling.

Signed-off-by: Dongjiu Geng <gengdongjiu1@gmail.com>
Change-Id: Ia7f9c5a0db36da03e5c6e6fb1270281f19924d77

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feat(juno): add mbedtls_asn1_get_len symbol in ROMlib

mbedtls_asn1_get_len() will be needed by the X.509 parser in an
upcoming patch.

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Ch

feat(juno): add mbedtls_asn1_get_len symbol in ROMlib

mbedtls_asn1_get_len() will be needed by the X.509 parser in an
upcoming patch.

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: I5609da000bbfc8a1503c298550ae3b0ba881fc96

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feat(fvp): add mbedtls_asn1_get_len symbol in ROMlib

mbedtls_asn1_get_len() will be needed by the X.509 parser in an
upcoming patch.

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Cha

feat(fvp): add mbedtls_asn1_get_len symbol in ROMlib

mbedtls_asn1_get_len() will be needed by the X.509 parser in an
upcoming patch.

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: I14310c80033a1142a94c0c4b54d63331479b643d

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