test(tc): test for AP/RSS interface for ROTPK

Adding new test for AP/RSS interface for reading ROTPK for
each 3 types of ROTPKs for: CCA, secure, and non-secure firmware.

Enabled by PLATFORM_TEST=r

test(tc): test for AP/RSS interface for ROTPK

Adding new test for AP/RSS interface for reading ROTPK for
each 3 types of ROTPKs for: CCA, secure, and non-secure firmware.

Enabled by PLATFORM_TEST=rss-rotpk.

Update to print output when AP/RSS interface platform tests
pass to be able to reuse expect script functionality in CI.

Change-Id: Icc50b090e18a272378751fda104d209738b5b70c
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

show more ...

Merge "feat(mt8188): modify APU DAPC permission" into integration

Merge changes from topic "xlnx_dtb_modification" into integration

* changes:
feat(versal-net): ddr address reservation in dtb at runtime
feat(versal): ddr address reservation in dtb at runtime

feat(mt8188): modify APU DAPC permission

We limited the r/w permission of some register groups for security
concerns. These regitser groups should not be accessed by domain 3 or
domain 5.

Change-Id

feat(mt8188): modify APU DAPC permission

We limited the r/w permission of some register groups for security
concerns. These regitser groups should not be accessed by domain 3 or
domain 5.

Change-Id: I2188da88d9e10a931d87bda14dc7dca46633dcd8
Signed-off-by: Chungying Lu <chungying.lu@mediatek.corp-partner.google.com>

show more ...

Merge "build(fpga): remove a710 from fpga build" into integration

Merge changes from topic "master" into integration

* changes:
fix(tc): rename macro to match PSA spec
fix(tc): Correct return type

feat(versal-net): ddr address reservation in dtb at runtime

When the TF-A is placed in DDR memory range, the DDR memory range
needs to be explicitly reserved in the default device tree.

A new build

feat(versal-net): ddr address reservation in dtb at runtime

When the TF-A is placed in DDR memory range, the DDR memory range
needs to be explicitly reserved in the default device tree.

A new build time parameter, XILINX_OF_BOARD_DTB_ADDR, is introduced.
The TF-A will reserve the DDR memory only when a valid DTB address
is provided to XILINX_OF_BOARD_DTB_ADDR during build.

Now the user has options, either manually reserve the desired DDR
address range for TF-A in device tree or let TF-A access and modify
the device tree, to reserve the DDR address range, in runtime using
the build parameter.

Change-Id: I45a5d9a8343ea8a19ea014a70023731de94d061a
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

show more ...

feat(versal): ddr address reservation in dtb at runtime

When the TF-A is placed in DDR memory range, the DDR memory range
needs to be explicitly reserved in the default device tree.

A new build tim

feat(versal): ddr address reservation in dtb at runtime

When the TF-A is placed in DDR memory range, the DDR memory range
needs to be explicitly reserved in the default device tree.

A new build time parameter, XILINX_OF_BOARD_DTB_ADDR, is introduced.
The TF-A will reserve the DDR memory only when a valid DTB address
is provided to XILINX_OF_BOARD_DTB_ADDR during build.

Now the user has options, either manually reserve the desired DDR
address range for TF-A in device tree or let TF-A access and modify
the device tree, to reserve the DDR address range, in runtime using
the build parameter.

Change-Id: I4442a90e1cab5a3a115f4eeb8a7e09e247189ff0
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

show more ...

Merge "fix(intel): resolved coverity checking" into integration

Merge changes from topic "psci-osi" into integration

* changes:
fix(sc7280): update system suspend in OS-initiated mode
fix(fvp): update system suspend in OS-initiated mode

fix(sc7280): update system suspend in OS-initiated mode

This patch fixes system suspend in OS-initiated mode by setting the
value of `last_at_pwrlvl` in the `psci_power_state_t` object to
`PLAT_MAX_

fix(sc7280): update system suspend in OS-initiated mode

This patch fixes system suspend in OS-initiated mode by setting the
value of `last_at_pwrlvl` in the `psci_power_state_t` object to
`PLAT_MAX_PWR_LVL`, which otherwise would result in undefined behavior.

This is conditionally compiled into the build depending on the value of
the `PSCI_OS_INIT_MODE` build option.

Change-Id: Ib9ff606b7eebd8a8224891a0d239a4e13311fe2a
Signed-off-by: Wing Li <wingers@google.com>

show more ...

fix(fvp): update system suspend in OS-initiated mode

This patch fixes system suspend in OS-initiated mode by setting the
value of `last_at_pwrlvl` in the `psci_power_state_t` object to
`PLAT_MAX_PWR

fix(fvp): update system suspend in OS-initiated mode

This patch fixes system suspend in OS-initiated mode by setting the
value of `last_at_pwrlvl` in the `psci_power_state_t` object to
`PLAT_MAX_PWR_LVL`, which otherwise would result in undefined behavior.

This is conditionally compiled into the build depending on the value of
the `PSCI_OS_INIT_MODE` build option.

Change-Id: Ia0fb1e68af9320370325642b17c4569e9580aa3a
Signed-off-by: Wing Li <wingers@google.com>

show more ...

fix(intel): resolved coverity checking

Coverity checking fix. Resolved unused value, deadcode and uninit.

1. CID: 395326
2. CID: 395327
3. CID: 395328
4. CID: 395329
5. CID: 395330

Signed-off

fix(intel): resolved coverity checking

Coverity checking fix. Resolved unused value, deadcode and uninit.

1. CID: 395326
2. CID: 395327
3. CID: 395328
4. CID: 395329
5. CID: 395330

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I86b8af28dc345542b142ce53e1935bb855888238

show more ...

Merge "fix(rcar): add mandatory fields in 'reserved-memory' node" into integration

build(fpga): remove a710 from fpga build

Currently we have a large series of errata_refactor patches pending
and they are all failing on arm_fpga build when we add errata_framework.

Errata framewor

build(fpga): remove a710 from fpga build

Currently we have a large series of errata_refactor patches pending
and they are all failing on arm_fpga build when we add errata_framework.

Errata framework can cause the size to grow and thus causing build
failure on bl31 size. This as of today is blocking us from
merging most of our changes as it will introduce a CI failure.

As an workaround we try to just reduce the arm_fpga build by a710
platform, we have a715 and a720 which should be ok I think.

Once everyone are available for further discussion we could revert this
change back and discuss further whats the right approach.

Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Change-Id: I96a821e10aaecf04db7407fb2df38012839bfb94

show more ...

Merge changes from topic "agilex5" into integration

* changes:
feat(intel): platform enablement for Agilex5 SoC FPGA
feat(intel): ccu driver for Agilex5 SoC FPGA
feat(intel): vab support for A

Merge changes from topic "agilex5" into integration

* changes:
feat(intel): platform enablement for Agilex5 SoC FPGA
feat(intel): ccu driver for Agilex5 SoC FPGA
feat(intel): vab support for Agilex5 SoC FPGA
feat(intel): sdmmc/nand/combo-phy/qspi driver for Agilex5 SoC FPGA
feat(intel): ddr driver for Agilex5 SoC FPGA
feat(intel): power manager for Agilex5 SoC FPGA
feat(intel): cold/warm reset and smp support for Agilex5 SoC FPGA
feat(intel): reset manager support for Agilex5 SoC FPGA
feat(intel): mailbox and SMC support for Agilex5 SoC FPGA
feat(intel): system manager support for Agilex5 SoC FPGA
feat(intel): memory controller support for Agilex5 SoC FPGA
feat(intel): clock manager support for Agilex5 SoC FPGA
feat(intel): mmc support for Agilex5 SoC FPGA
feat(intel): uart support for Agilex5 SoC FPGA
feat(intel): pinmux, peripheral and Handoff support for Agilex5 SoC FPGA

show more ...

Merge changes from topic "imx93_basic_support" into integration

* changes:
docs(imx9): add imx93 platform
feat(imx93): add OPTEE support
feat(imx93): protect OPTEE memory to secure access only

Merge changes from topic "imx93_basic_support" into integration

* changes:
docs(imx9): add imx93 platform
feat(imx93): add OPTEE support
feat(imx93): protect OPTEE memory to secure access only
feat(imx93): add cpuidle and basic suspend support
feat(imx93): add reset & poweroff support
feat(imx93): allow SoC masters access to system TCM
feat(imx93): update the ocram trdc config for did10
feat(imx93): add the basic support
feat(imx93): add the trdc driver
build(changelog): add new scopes for nxp imx platform

show more ...

Merge "feat(qemu): add "neoverse-v1" cpu support" into integration

Merge changes from topic "mb/mb-rss-refactor" into integration

* changes:
refactor(tc): update RSS driver inteface calls
refactor(fvp): update RSS driver inteface calls
refactor(rss): make RSS

Merge changes from topic "mb/mb-rss-refactor" into integration

* changes:
refactor(tc): update RSS driver inteface calls
refactor(fvp): update RSS driver inteface calls
refactor(rss): make RSS driver standalone for Measured Boot

show more ...

fix(tc): rename macro to match PSA spec

Update 'PSA_INITIAL_ATTEST_TOKEN_MAX_SIZE' to
'PSA_INITIAL_ATTEST_MAX_TOKEN_SIZE' which is defined
in the PSA Certified Attestation API spec.

Change-Id: I583

fix(tc): rename macro to match PSA spec

Update 'PSA_INITIAL_ATTEST_TOKEN_MAX_SIZE' to
'PSA_INITIAL_ATTEST_MAX_TOKEN_SIZE' which is defined
in the PSA Certified Attestation API spec.

Change-Id: I5837fea552e6fe18a203412eb90d41e2f90ad6f1
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>

show more ...

fix(tc): Correct return type

The fact that this was void instead of int, as required, caused
the test-running code to assume that the tests always failed.

Fixing the return type fixes the always-te

fix(tc): Correct return type

The fact that this was void instead of int, as required, caused
the test-running code to assume that the tests always failed.

Fixing the return type fixes the always-tests-failing bug.

Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
Change-Id: Ief55fe15c437c87dac1d03419a8e148f5d864b8d

show more ...

Merge "fix(n1sdp): configure platform specific secure SPIs" into integration

feat(qemu): add "neoverse-v1" cpu support

Add support to qemu "neoverse-v1" cpu for "qemu" ('virt') platform.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I4821115b5

feat(qemu): add "neoverse-v1" cpu support

Add support to qemu "neoverse-v1" cpu for "qemu" ('virt') platform.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I4821115b54ca596fe27cb9d74a95429cd3cb21d9

show more ...

Merge "feat(qemu): add "neoverse-v1" cpu support" into integration

feat(intel): platform enablement for Agilex5 SoC FPGA

This patch is used to enable platform enablement for
Agilex5 SoC FPGA.

New feature:
1. Added ATF->Zephyr boot option
2. Added xlat_v2 for MMU

feat(intel): platform enablement for Agilex5 SoC FPGA

This patch is used to enable platform enablement for
Agilex5 SoC FPGA.

New feature:
1. Added ATF->Zephyr boot option
2. Added xlat_v2 for MMU
3. Added ATF->Linux boot option
4. Added SMP support
5. Added HPS bridges support
6. Added EMULATOR support
7. Added DDR support
8. Added GICv3 Redistirbution init
9. Added SDMMC/NAND/Combo Phy support
10. Updated GIC as secure access
11. Added CCU driver support
12. Updated product name -> Agilex5
13. Updated register address based on y22ww52.2 RTL
14. Updated system counter freq to 400MHz

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Ice82f3e4535527cfd01500d4d528402985f72009

show more ...