| 8e59b9f4 | 17-May-2023 |
Jit Loon Lim <jit.loon.lim@intel.com> |
feat(intel): mailbox and SMC support for Agilex5 SoC FPGA
This patch is used to enable mailbox and SMC support
for Agilex5 SoC FPGA.
1. Enabled mailbox and SMC support.
2. Updated product name ->
feat(intel): mailbox and SMC support for Agilex5 SoC FPGA
This patch is used to enable mailbox and SMC support
for Agilex5 SoC FPGA.
1. Enabled mailbox and SMC support.
2. Updated product name -> Agilex5
3. Updated register address based on y22ww52.2 RTL
4. Updated TSN register base address
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I152bee5668b96ef599ded09945167f27a71f23fe
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|
| 76184031 | 17-May-2023 |
Jit Loon Lim <jit.loon.lim@intel.com> |
feat(intel): system manager support for Agilex5 SoC FPGA
This patch is used to implement system manager data
support for Agilex5 SoC FPGA.
1. Initial SM bring up
2. Support Candence SDMMC/NAND/CO
feat(intel): system manager support for Agilex5 SoC FPGA
This patch is used to implement system manager data
support for Agilex5 SoC FPGA.
1. Initial SM bring up
2. Support Candence SDMMC/NAND/COMBO PHY
3. Updated product name -> Agilex5
4. Updated register address based on y22ww52.2 RTL
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I12712bddfb67e36a2bf56d2d98ea4ca3037f0a82
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|
| 18adb4ef | 17-May-2023 |
Jit Loon Lim <jit.loon.lim@intel.com> |
feat(intel): memory controller support for Agilex5 SoC FPGA
This patch is used to enable memory controller support
for Agilex5 SoC FPGA.
1. Added memory controller support.
2. Updated product name
feat(intel): memory controller support for Agilex5 SoC FPGA
This patch is used to enable memory controller support
for Agilex5 SoC FPGA.
1. Added memory controller support.
2. Updated product name -> Agilex5
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I8381b82eeed939b970a7410a6181a514f2c90caa
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|
| 1b1a3eb1 | 17-May-2023 |
Jit Loon Lim <jit.loon.lim@intel.com> |
feat(intel): clock manager support for Agilex5 SoC FPGA
This patch is used to enable clock manager support
for Agilex5 SoC FPGA.
1. Added clock manager support.
2. Updated product name -> Agilex5
feat(intel): clock manager support for Agilex5 SoC FPGA
This patch is used to enable clock manager support
for Agilex5 SoC FPGA.
1. Added clock manager support.
2. Updated product name -> Agilex5
3. Updated register address based on y22ww52.2 RTL
4. Standardized handoff handler.
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Ic4c57a1955136ef7d22253c3ca52226e5620751b
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|
| 4a577da6 | 17-May-2023 |
Jit Loon Lim <jit.loon.lim@intel.com> |
feat(intel): mmc support for Agilex5 SoC FPGA
This patch is used to enable MMC support for
Agilex5 SoC FPGA.
1. Added MMC support.
2. Updated product name -> Agilex5
3. Updated register address b
feat(intel): mmc support for Agilex5 SoC FPGA
This patch is used to enable MMC support for
Agilex5 SoC FPGA.
1. Added MMC support.
2. Updated product name -> Agilex5
3. Updated register address based on y22ww52.2 RTL
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I47f5c7f063fc443f29c2af612121abe672ed422b
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|
| 34971f81 | 17-May-2023 |
Jit Loon Lim <jit.loon.lim@intel.com> |
feat(intel): uart support for Agilex5 SoC FPGA
This patch is used to enable UART & WDT support
for Agilex5 SoC FPGA.
1. Added watchdog support.
2. Updated product name -> Agilex5
Signed-off-by:
feat(intel): uart support for Agilex5 SoC FPGA
This patch is used to enable UART & WDT support
for Agilex5 SoC FPGA.
1. Added watchdog support.
2. Updated product name -> Agilex5
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I9346cfde6e033026e4c1e612250e9521bc6b0d47
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|
| fcbb5cf7 | 17-May-2023 |
Jit Loon Lim <jit.loon.lim@intel.com> |
feat(intel): pinmux, peripheral and Handoff support for Agilex5 SoC FPGA
This patch is used to enable pinmux, peripheral and handoff support
for Agilex5 SoC FPGA.
1. Initial handoff bring up
2. Ad
feat(intel): pinmux, peripheral and Handoff support for Agilex5 SoC FPGA
This patch is used to enable pinmux, peripheral and handoff support
for Agilex5 SoC FPGA.
1. Initial handoff bring up
2. Added power manager handoff implementation
3. Added sdram handoff implementation
4. Updated product name -> Agilex5
5. Updated register address based on y22ww52.2 RTL
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I4b0176bc86c57823127bf41086306015d702577d
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|
| e7644eb6 | 04-Jul-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "chore(xilinx): reorder include files as per TF-A guidelines" into integration |
| 38a05485 | 04-Jul-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "fix(versal-net): correct device node indexes" into integration |
| 106aa54d | 09-Jun-2023 |
Jit Loon Lim <jit.loon.lim@intel.com> |
fix(intel): fix ncore ccu snoop dvm enable bug
Incorrect value stored in Coherent Subsystem ACE DVM Snoop Enable
register (CSADSER0). Set individual bit othervise previous value
is overwritten.
Sig
fix(intel): fix ncore ccu snoop dvm enable bug
Incorrect value stored in Coherent Subsystem ACE DVM Snoop Enable
register (CSADSER0). Set individual bit othervise previous value
is overwritten.
Signed-off-by: Anders Hedlund <anders.hedlund@windriver.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Ib72fed261cbc3076ce385e19c4a5fa8e9e8b9924
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|
| 7b0c95ab | 25-May-2023 |
Werner Lewis <werner.lewis@arm.com> |
fix(n1sdp): configure platform specific secure SPIs
Previous implementation used common CSS interrupts, which do not match
the N1SDP platform interrupt map. Updated to configure Secure
interrupts ac
fix(n1sdp): configure platform specific secure SPIs
Previous implementation used common CSS interrupts, which do not match
the N1SDP platform interrupt map. Updated to configure Secure
interrupts according to the N1SDP TRM and InfraSYSDESIGN4.0
specification. Additionally, unused definitions from legacy interrupt
configuration are removed.
Signed-off-by: Werner Lewis <werner.lewis@arm.com>
Change-Id: I3dd4bcd4875e138057c62d937572d446b8f88471
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|
| 214de62c | 04-Jul-2023 |
Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> |
feat(qemu): add "neoverse-v1" cpu support
Add support to qemu "neoverse-v1" cpu for "qemu_sbsa" ('sbsa-ref')
platform.
Change-Id: Id710e2b960e7938d2dbe7a88d9e158a7009fc3d1
Signed-off-by: Marcin Jus
feat(qemu): add "neoverse-v1" cpu support
Add support to qemu "neoverse-v1" cpu for "qemu_sbsa" ('sbsa-ref')
platform.
Change-Id: Id710e2b960e7938d2dbe7a88d9e158a7009fc3d1
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
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|
| cd89a704 | 16-Jun-2023 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
refactor(tc): update RSS driver inteface calls
In order to comply with the previous RSS driver change,
interface calls have been updated.
Change-Id: I645f6e8638cedfa6ff92d07b93cbaf38bdb2e09f
Signed
refactor(tc): update RSS driver inteface calls
In order to comply with the previous RSS driver change,
interface calls have been updated.
Change-Id: I645f6e8638cedfa6ff92d07b93cbaf38bdb2e09f
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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|
| a99a378d | 16-Jun-2023 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
refactor(fvp): update RSS driver inteface calls
In order to comply with the previous RSS driver change,
interface calls have been updated.
Change-Id: I0a1f3c6a6f8017468d86903cc0158805c6461c28
Signe
refactor(fvp): update RSS driver inteface calls
In order to comply with the previous RSS driver change,
interface calls have been updated.
Change-Id: I0a1f3c6a6f8017468d86903cc0158805c6461c28
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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|
| 8e31faa0 | 30-Jun-2023 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes from topic "xlnx_handoff_changes" into integration
* changes:
chore(xilinx): update warning message
feat(versal-net): add cluster check in handoff parameters
feat(versal-net): ge
Merge changes from topic "xlnx_handoff_changes" into integration
* changes:
chore(xilinx): update warning message
feat(versal-net): add cluster check in handoff parameters
feat(versal-net): get the handoff params using IPI
chore(xilinx): replace fsbl with xbl
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|
| 66b5620c | 28-Jun-2023 |
Jay Buddhabhatti <jay.buddhabhatti@amd.com> |
fix(versal-net): correct device node indexes
Currently, the peripheral node indexes are incorrect
for Versal NET due to which incorrect node error is
generated and permission to set the device as wa
fix(versal-net): correct device node indexes
Currently, the peripheral node indexes are incorrect
for Versal NET due to which incorrect node error is
generated and permission to set the device as wakeup
source is failed. Correct Versal NET peripheral node
indexes to fix above issue.
Fixes: 662aafd6475e ("feat(xilinx): add device node indexes")
Change-Id: I4a2d76f375645e13512599a0272d9322ff6fafd3
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
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|
| 1c62cc7f | 30-Jun-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "fix(mediatek): support saving/restoring GICR registers" into integration |
| a0a4d86c | 22-Jun-2023 |
Akshay Belsare <akshay.belsare@amd.com> |
chore(xilinx): update warning message
Update the Warning message to be more informative
about the warning being printed.
Change-Id: I923dc5dd760908844d5e1ac8542fd1b04c9f0af5
Signed-off-by: Akshay B
chore(xilinx): update warning message
Update the Warning message to be more informative
about the warning being printed.
Change-Id: I923dc5dd760908844d5e1ac8542fd1b04c9f0af5
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
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|
| 01c8c6a5 | 15-Jun-2023 |
Akshay Belsare <akshay.belsare@amd.com> |
feat(versal-net): add cluster check in handoff parameters
Versal NET platform supports multiple cpu clusters and the cluster
information for every partition contaning firmware component
is being pas
feat(versal-net): add cluster check in handoff parameters
Versal NET platform supports multiple cpu clusters and the cluster
information for every partition contaning firmware component
is being passed by PLM through handoff parameters to TF-A.
Function implementation for getting cluster value for the firmware
component partition in TF-A and check for the firmware component
being targeted to be executed on Cluster 0.
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Change-Id: I8622699e12b0a9cda83ae46e2ad0a038ca377fda
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|
| a36ac40c | 07-Mar-2023 |
Akshay Belsare <akshay.belsare@amd.com> |
feat(versal-net): get the handoff params using IPI
Use the IPI command GET_HANDOFF_PARAM to get the PLM to TF-A handoff
parameters. The BL32/BL33 information from the handoff parameters will
be used
feat(versal-net): get the handoff params using IPI
Use the IPI command GET_HANDOFF_PARAM to get the PLM to TF-A handoff
parameters. The BL32/BL33 information from the handoff parameters will
be used by TF-A.
If no valid PLM to TF-A handoff parameters are available then,
the TF-A will fall back to the build time information or defaults
set in the TF-A for BL32/BL33.
Once the bootmode identification is supported the default configuration
will be done only for JTAG and for all other bootmodes PLM to TF-A
handoff parameters will be used.
Change-Id: Ia2204fe30fea6f32b4e5d2610820217e6ed23e4d
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
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|
| b9d26cd3 | 08-Jun-2023 |
Prasad Kummari <prasad.kummari@amd.com> |
chore(xilinx): replace fsbl with xbl
The handoff functionality is common between platforms and all
platforms do not use fsbl terminology. Renaming handoff related code
to generic naming.
Signed-off
chore(xilinx): replace fsbl with xbl
The handoff functionality is common between platforms and all
platforms do not use fsbl terminology. Renaming handoff related code
to generic naming.
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: Ic250af927f33c4fecbc2e6bab01b83a6dd2aab52
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
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|
| 27a0be77 | 31-May-2022 |
Clement Faure <clement.faure@nxp.com> |
feat(imx93): add OPTEE support
Add OPTEE support for imx93 platform.
Add support for the device tree overlay.
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Jacky Bai <ping.bai
feat(imx93): add OPTEE support
Add OPTEE support for imx93 platform.
Add support for the device tree overlay.
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I99c7819665f8f746b0dd7941fb83dbec9d8651de
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|
| f560f843 | 27-Sep-2022 |
Ye Li <ye.li@nxp.com> |
feat(imx93): protect OPTEE memory to secure access only
Configure TRDC_NIC MRC0 to protect OPTEE DDR memory to secure
access only from A55 cores and other peripherals' masters.
Signed-off-by: Ye Li
feat(imx93): protect OPTEE memory to secure access only
Configure TRDC_NIC MRC0 to protect OPTEE DDR memory to secure
access only from A55 cores and other peripherals' masters.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Ie5363ecff67e3183fbde998a0bba93df4c099e1f
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|
| 422d30c6 | 07-Jun-2023 |
Jacky Bai <ping.bai@nxp.com> |
feat(imx93): add cpuidle and basic suspend support
Add cpuidle and basic suspend support. For now only
core & cluster will be put into low power mode when
system suspend.
Signed-off-by: Jacky Bai <
feat(imx93): add cpuidle and basic suspend support
Add cpuidle and basic suspend support. For now only
core & cluster will be put into low power mode when
system suspend.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Ife0b6dc48738ae7a2322d6a7f6342ffe15d35342
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|
| cf7ef4c7 | 25-May-2023 |
Jacky Bai <ping.bai@nxp.com> |
feat(imx93): add reset & poweroff support
Add system reset & system power off support on i.MX93.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Id180461541a1b3f73b2dc00c9cad33f484c145e6 |