fix(versal-net): add redundant call to avoid glitches

Add redundant macro call to increase security by making
code glitch immune as security operations might be
called with the IPI command.

Signed-

fix(versal-net): add redundant call to avoid glitches

Add redundant macro call to increase security by making
code glitch immune as security operations might be
called with the IPI command.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I84d84cca258b7cd981f62816c51032341e19095c

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fix(versal-net): change flag to increase security

Currently security flag is set to SECURE by default and
is changed to NON_SECURE if NS system is detected. In this
case NS system may access secure

fix(versal-net): change flag to increase security

Currently security flag is set to SECURE by default and
is changed to NON_SECURE if NS system is detected. In this
case NS system may access secure system if condition check
gets skipped due to glitches.

So, initialize security_flag to NON_SECURE_FLAG and switch
to SECURE_FLAG if the TrustZone bit is detected to be
in more secure state.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I7af54465bd8744ba97a58c02607631ee23619d47

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refactor(ethos-n): move build flags to ethosn_npu.mk

The build flags to enable the Arm(R) Ethos(TM)-N NPU driver are in arm
platform specific make files i.e. plat/arm/common/arm_common.mk. These
fla

refactor(ethos-n): move build flags to ethosn_npu.mk

The build flags to enable the Arm(R) Ethos(TM)-N NPU driver are in arm
platform specific make files i.e. plat/arm/common/arm_common.mk. These
flags are renamed and moved to ethosn_npu.mk. Other source and make
files are changed to reflect the changes in these flags.

Signed-off-by: Rajasekaran Kalidoss <rajasekaran.kalidoss@arm.com>
Change-Id: I6fd20225343c574cb5ac1f0f32ff2fc28ef37ea6

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Merge changes from topic "mb/mb-signer-id" into integration

* changes:
feat(qemu): add dummy plat_mboot_measure_key() function
docs(rss): update RSS doc for signer-ID
feat(imx): add dummy 'pla

Merge changes from topic "mb/mb-signer-id" into integration

* changes:
feat(qemu): add dummy plat_mboot_measure_key() function
docs(rss): update RSS doc for signer-ID
feat(imx): add dummy 'plat_mboot_measure_key' function
feat(tc): implement platform function to measure and publish Public Key
feat(auth): measure and publicise the Public Key
feat(fvp): implement platform function to measure and publish Public Key
feat(fvp): add public key-OID information in RSS metadata structure
feat(auth): add explicit entries for key OIDs
feat(rss): set the signer-ID in the RSS metadata
feat(auth): create a zero-OID for Subject Public Key
docs: add details about plat_mboot_measure_key function
feat(measured-boot): introduce platform function to measure and publish Public Key

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Merge "chore(xilinx): reorder headers in assembly files" into integration

Merge "chore(xilinx): correct kernel doc warnings for missing functions" into integration

Merge changes from topic "xlnx_zynmp_tsp" into integration

* changes:
chore(zynqmp): remove unused configuration from TSP
fix(zynqmp): resolve runtime error in TSP

Merge "fix(xilinx): add headers to resolve compile time issue" into integration

fix(xilinx): add headers to resolve compile time issue

Add common/debug.h and libfdt.h files to the common file
for XILINX_OF_BOARD_DTB_ADDR configuration.

Signed-off-by: Akshay Belsare <akshay.bel

fix(xilinx): add headers to resolve compile time issue

Add common/debug.h and libfdt.h files to the common file
for XILINX_OF_BOARD_DTB_ADDR configuration.

Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Change-Id: I577cc018eda34e186e48594a62c54eb55f11bbd3

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fix(bl32): always include arm_arch_svc in SP_MIN

The PSCI_FEATURES call implementation in TF-A always indicates support
for SMCCC_VERSION, but only BL31 ensures that the corresponding Arm
Architectu

fix(bl32): always include arm_arch_svc in SP_MIN

The PSCI_FEATURES call implementation in TF-A always indicates support
for SMCCC_VERSION, but only BL31 ensures that the corresponding Arm
Architecture Service (arm_arch_svc) is really included in the build.
For SP_MIN only stm32mp1 currently includes it in the platform-specific
make file.

This means that it is easily possible to build configurations that
violate the PSCI/SMCCC specification. On Linux this leads to incorrect
detection of the SMC Calling Convention when using SP_MIN:

[ 0.000000] psci: SMC Calling Convention v65535.65535

Fix this by always including the Arm Architecture Service in SP_MIN
builds. This allows Linux to detect the convention correctly:

[ 0.000000] psci: SMC Calling Convention v1.4

Change-Id: Iaa3076c162b7a55633ec1e27eb5c44d22f8eb2a1
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

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fix(errata-abi): added Neoverse N2 to Errata ABI list

added the missing Neoverse N2 flag required for
enabling Neoverse N2 CPU in Errata ABI

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm

fix(errata-abi): added Neoverse N2 to Errata ABI list

added the missing Neoverse N2 flag required for
enabling Neoverse N2 CPU in Errata ABI

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I06c6fa67e2f1ccc053f1b1b9261e189c56f4347a

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Merge "fix(imx8m): make IMX_BOOT_UART_BASE autodetection option more obvious" into integration

fix(xilinx): remove clock_setrate and clock_getrate api

As per the current code base, PM_CLOCK_SETRATE and PM_CLOCK_GETRATE
APIs are not supported for the runtime operations in the firmware and
the

fix(xilinx): remove clock_setrate and clock_getrate api

As per the current code base, PM_CLOCK_SETRATE and PM_CLOCK_GETRATE
APIs are not supported for the runtime operations in the firmware and
the TF-A it is already returning an error when there is any request
to access these APIs. So, just removing the unused code to avoid the
confusion around these APIs.

Also, there is no issue with the backward compatibility as these APIs
were never used since implemented. Hence no need to bump up the
version of the feature check API as well.

Signed-off-by: Ronak Jain <ronak.jain@amd.com>
Change-Id: I444f973e62cd25aae2e7f697d808210b265106ad

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fix(imx8m): make IMX_BOOT_UART_BASE autodetection option more obvious

Switch from IMX_BOOT_UART_BASE=0 to IMX_BOOT_UART_BASE=auto to make it
more obvious that the detection is based on the runtime a

fix(imx8m): make IMX_BOOT_UART_BASE autodetection option more obvious

Switch from IMX_BOOT_UART_BASE=0 to IMX_BOOT_UART_BASE=auto to make it
more obvious that the detection is based on the runtime autodetection.

In addition this moves the evaluation of IMX_BOOT_UART_BASE into the
makefile which removes the ugly conditional compilation as well.

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Change-Id: I92c13607bf81c6267f4b6aee829d74902b7f72d2

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feat(rdn2): enable Neoverse N2 CPU error handling support

Defines N2 CPU RAS error for RD-N2 platform variants. Enables N2 CPU
error handling on RD-N2 platform variants.

Signed-off-by: Omkar Anand

feat(rdn2): enable Neoverse N2 CPU error handling support

Defines N2 CPU RAS error for RD-N2 platform variants. Enables N2 CPU
error handling on RD-N2 platform variants.

Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
Change-Id: If9378064c41e0d14e6c789c71f8def594f89e220

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feat(sgi): firmware first error handling for Neoverse N2 CPU

RD-N2 platform variants have Neoverse N2 CPU that supports RAS
extensions. N2 CPU has error node that captures the faults occurring on
L1

feat(sgi): firmware first error handling for Neoverse N2 CPU

RD-N2 platform variants have Neoverse N2 CPU that supports RAS
extensions. N2 CPU has error node that captures the faults occurring on
L1, L2 tag and data RAMs. This node captures the error information in
its error records and generates fault handling interrupt on error event.

This patch adds reference implementation to demonstrate firmware-first
error handling of 1-bit CE that occur on CPU. On error event the error
handler reads the error records and ELx context information and forwards
it to secure partition. Secure partition creates a CPER record from this
error information. Finally the handler notifies the OS about the RAS
error using the SDEI notification mechanism.

Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
Change-Id: I769550efee10b9a3d89056bca4bfeb2db4708998

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feat(arm): enable FHI PPI interrupt to report CPU errors

To handle the core corrected errors in the firmware, the FHI PPI
interrupt has to be enabled on all the cores. At boot, when the RAS
framewor

feat(arm): enable FHI PPI interrupt to report CPU errors

To handle the core corrected errors in the firmware, the FHI PPI
interrupt has to be enabled on all the cores. At boot, when the RAS
framework is initialized, only primary core is up and hence core FHI PPI
interrupt is enabled only on primary core. This patch adds support to
configure and enable core FHI interrupt for all the secondary cores as
part of their boot sequence.

Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
Change-Id: I4b25152cb498fe975b9c770babb25aa9e01f9656

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chore(zynqmp): remove unused configuration from TSP

In ZynqMP, the function zynqmp_config_setup() is common between bl31
and bl32(TSP). This function initializes IPI configuration and
prints the chi

chore(zynqmp): remove unused configuration from TSP

In ZynqMP, the function zynqmp_config_setup() is common between bl31
and bl32(TSP). This function initializes IPI configuration and
prints the chip idcode and revision on the console, which is already
done in bl31 and redundant in bl32(TSP).

Remove the legacy code, reading the chip idcode and
revision information through direct register read.

Change-Id: I5da8e75a597ac9c4e1b56346e065d29e2be8787f
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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fix(zynqmp): resolve runtime error in TSP

TSP(bl32) requires secure interrupts to be handled at S-EL1.
Enable the ZynqMP to handle secure interrupts in S-EL1 by setting
GICV2_G0_FOR_EL3 to 0 in case

fix(zynqmp): resolve runtime error in TSP

TSP(bl32) requires secure interrupts to be handled at S-EL1.
Enable the ZynqMP to handle secure interrupts in S-EL1 by setting
GICV2_G0_FOR_EL3 to 0 in case of SPD=tspd build option.

For ZYNQMP_WDT_RESTART build option GICV2_G0_FOR_EL3 needs to be
enabled and thus for ZynqMP GICV2_G0_FOR_EL3 is set to 1 by default.
On GICv2, when GICV2_G0_FOR_EL3 is set to 1, Group 0 interrupts
target EL3. This allows GICv2 platforms to enable features requiring
EL3 interrupt type.

This also means that all GICv2 Group 0 interrupts are delivered
to EL3, and the Secure Payload interrupts needs to be synchronously
handed over to Secure EL1 for handling.

Change-Id: I7eb72c6588ab41730a74ece261050840646de037
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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chore(xilinx): reorder headers in assembly files

In tf-a-ci-scripts repo, change commit 8ffa3d571b(ci(static-checks):
correct include order for *.S macro headers) provides a fix related
to header fi

chore(xilinx): reorder headers in assembly files

In tf-a-ci-scripts repo, change commit 8ffa3d571b(ci(static-checks):
correct include order for *.S macro headers) provides a fix related
to header file include order in assembly files. With the above fix,
improper header order in assembly files has been detected.

Reorder the header includes in assembly files as per the update
in tf-a-ci-scripts.

Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: I4a4f3c5bb73886dae234160b893470443f1424fc

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chore(xilinx): correct kernel doc warnings for missing functions

In commit b9d26cd3c4 ("chore(xilinx): replace fsbl with xbl"),
function and variable names were changed, but the corresponding
functi

chore(xilinx): correct kernel doc warnings for missing functions

In commit b9d26cd3c4 ("chore(xilinx): replace fsbl with xbl"),
function and variable names were changed, but the corresponding
function name in the functional documentation comments is not updated.
Update the function and variable names as per the above commit.

Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: I7b777c21fe3673d29f809bf923eba38749f2c024

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feat(allwinner): use reset through scpi for warm/soft reset

On systems with SCP (running crust) scpi_system_reboot action
performs board-level (PMIC) reboot. This doesn't preserve RAM content
on A64

feat(allwinner): use reset through scpi for warm/soft reset

On systems with SCP (running crust) scpi_system_reboot action
performs board-level (PMIC) reboot. This doesn't preserve RAM content
on A64 PinePhone at least.

warm/soft system reset without RAM reset is required to get
pstore (persistent storage) in RAM working with Linux kernel. That is
very useful for oops/panic logging for post mortem analysis.

scpi_system_reset action performs reset via SoC reset (using watchdog)
and RAM content is preserved in this case. Linux kernel detects
system_reset2 support and uses it for warm reset automatically.

Change-Id: I1c21aa8f27c8e0395e2326034788693b59b80bc4
Signed-off-by: Andrey Skvortsov <andrej.skvortzov@gmail.com>

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Merge "feat(nuvoton): added support for npcm845x chip" into integration

feat(qemu): add dummy plat_mboot_measure_key() function

Adds a dummy implementation of the plat_mboot_measure_key() function for
QEMU platform.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.

feat(qemu): add dummy plat_mboot_measure_key() function

Adds a dummy implementation of the plat_mboot_measure_key() function for
QEMU platform.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Change-Id: I64c1c751348c04cd359c075fc15a0d180ff55918

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feat(imx): add dummy 'plat_mboot_measure_key' function

Added dummy implementation of 'plat_mboot_measure_key'
function for IMX platform.

Change-Id: Ib41fd86a9da330f62561707bda7d16f2825c0a7f
Signed-

feat(imx): add dummy 'plat_mboot_measure_key' function

Added dummy implementation of 'plat_mboot_measure_key'
function for IMX platform.

Change-Id: Ib41fd86a9da330f62561707bda7d16f2825c0a7f
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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