fix(xilinx): don't reserve 1 more byte

The commit f123b91fddfc ("fix(versal): fix BLXX memory
limits for user defined values") and commit a80da3899a5e
("fix(versal-net): fix BLXX memory limits for u

fix(xilinx): don't reserve 1 more byte

The commit f123b91fddfc ("fix(versal): fix BLXX memory
limits for user defined values") and commit a80da3899a5e
("fix(versal-net): fix BLXX memory limits for user defined
values") fixed issue regarding linker alignment section.
But removing -1 logic is not reflected in plat_fdt() memory
reservation code.
That's why remove +1 from prepare_dtb() not to generate a reserved
memory node with bigger size which ends up with reserving more
space than actually requested by a full featured bootloader or OS.

Change-Id: I0a646cee7d5a55157a6eb1b672c2edbe89e6a57f
Signed-off-by: Michal Simek <michal.simek@amd.com>

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Merge "fix(arm/fpga): enable CPU features required for ARMv9.2 cores" into integration

feat(morello): add cpuidle support

This patch adds necessary device-tree idle state definitions and enables
relevant platform makefile options.

Co-authored-by: Karl Meakin <karl.meakin@arm.com>
Sig

feat(morello): add cpuidle support

This patch adds necessary device-tree idle state definitions and enables
relevant platform makefile options.

Co-authored-by: Karl Meakin <karl.meakin@arm.com>
Signed-off-by: sahil <sahil@arm.com>
Change-Id: Iaf95867095f0514ec3994b9c9efd9756ed49ef43

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Merge "fix(ti): fix TISCI API changes during refactor" into integration

feat(imx8m): move the gpc reg & macro to a separate header file

move the gpc reg offset, bit define & macro to a separate header
file for code reuse.

This fixes suspend to mem on i.MX8M Plus too, s

feat(imx8m): move the gpc reg & macro to a separate header file

move the gpc reg offset, bit define & macro to a separate header
file for code reuse.

This fixes suspend to mem on i.MX8M Plus too, since the register
layout is different there.

Change-Id: Ibec60c3a68ffa8c378de5334577a7b0e463ca875
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Marek Vasut <marex@denx.de> # Upgrade to latest, update commit message

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feat(imx8m): add more dram pll setting

Add DRAM PLL frequency setting for 3732mts & 3733mts.

Change-Id: I74feab2185376bbb84826d7ee79b5e25cbc4d263
Signed-off-by: Marek Vasut <marex@denx.de>

fix(arm/fpga): enable CPU features required for ARMv9.2 cores

Similar to the FVP and QEMU, the Arm FPGA systems come with different
CPU cores, and gain new features over time.

Add a list of ARMv9.2

fix(arm/fpga): enable CPU features required for ARMv9.2 cores

Similar to the FVP and QEMU, the Arm FPGA systems come with different
CPU cores, and gain new features over time.

Add a list of ARMv9.2 features that require TF-A enablement to be usable
from non-secure world. Their existence will be detected at runtime, so
supporting all those features is not required for using the build.

This fixes the Linux kernel booting on a ARMv9.2 FPGA core.

Change-Id: Ie93c32b13ce4f9968081bf38296cd45edad0a928
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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fix(xilinx): update dtb when dtb address and tf-a ddr flow is used

Memory reservation in dtb will be done only when TF-A runs from
ddr and dtb load address is provided.
Otherwise prepare_dtb will si

fix(xilinx): update dtb when dtb address and tf-a ddr flow is used

Memory reservation in dtb will be done only when TF-A runs from
ddr and dtb load address is provided.
Otherwise prepare_dtb will simply return.
Empty definition of prepare_dtb is removed.

Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Change-Id: Ie8a3ec51d60a7389831cfe6a112f722777930623

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fix(versal): use correct macro name for ocm base address

In absence of definition, PLAT_OCM_BASE is always 0
and IS_TFA_IN_OCM(x) always returns true irrespective
of address passed to it. Reasoning

fix(versal): use correct macro name for ocm base address

In absence of definition, PLAT_OCM_BASE is always 0
and IS_TFA_IN_OCM(x) always returns true irrespective
of address passed to it. Reasoning is as mentioned in
Refer section 4.2.3 in
https://gcc.gnu.org/onlinedocs/gcc-3.0.2/cpp_4.html
Due to this,functionality for reservation of TF-A DDR memory in
dtb is never executed.

Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Change-Id: Iafb6b7c6aec29bba22f8f7a8395f9caf97548157

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refactor(arm): avoid setting HASH_PREREQUISITES for a build without ROT_KEY

In the absence of ROT_KEY option, there is no need to populate
HASH_PREREQUISITES as the build system uses the hash file s

refactor(arm): avoid setting HASH_PREREQUISITES for a build without ROT_KEY

In the absence of ROT_KEY option, there is no need to populate
HASH_PREREQUISITES as the build system uses the hash file specified by
ARM_ROTPK_HASH directly.

Change-Id: Ib08f53b182b8446bbc430f2608471c7dfdc0e58c
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge "refactor(ast2700): update memory layout" into integration

refactor(ast2700): update memory layout

Update the memory layout for both BL31 and BL32 FW based on
the 1GB DRAM space of the AST2700 EVB.

Minor:
- Use SZ_xx macro to define size for better readab

refactor(ast2700): update memory layout

Update the memory layout for both BL31 and BL32 FW based on
the 1GB DRAM space of the AST2700 EVB.

Minor:
- Use SZ_xx macro to define size for better readability

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Change-Id: I6d8285bd675321f615bb67cdd27bb4b6cb4c8b16

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Merge "feat(cpus): add support for Nevis CPU" into integration

feat(cpus): add support for Nevis CPU

Adding basic CPU library code to support Nevis CPU

Change-Id: I399cc9b7b2d907b02b76ea2a3e5abb54e28fbf6c
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.co

feat(cpus): add support for Nevis CPU

Adding basic CPU library code to support Nevis CPU

Change-Id: I399cc9b7b2d907b02b76ea2a3e5abb54e28fbf6c
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>

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chore(npcm845x): remove pauth_helpers.S additions in platform makefile

Currently 'pauth_helpers.S' is added if pauth is enabled from main
level makefile.

Change-Id: I33800e280daea6dba6d11e2c494101b

chore(npcm845x): remove pauth_helpers.S additions in platform makefile

Currently 'pauth_helpers.S' is added if pauth is enabled from main
level makefile.

Change-Id: I33800e280daea6dba6d11e2c494101b369cd8a0b
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge "fix(nuvoton): fix typo in platform.mk" into integration

Merge "build(bl32): added check for AARCH32_SP" into integration

build(bl32): added check for AARCH32_SP

If AACRH32_SP is not specified, it causes the DEFAULT_LINKER_SCRIPT
variable to be empty, and then the linker takes the variable following
it as if it was the

build(bl32): added check for AARCH32_SP

If AACRH32_SP is not specified, it causes the DEFAULT_LINKER_SCRIPT
variable to be empty, and then the linker takes the variable following
it as if it was the linker script, which is not one. This patch
addresses that issue by requiring the AARCH32_SP variable to be set
before continuing.

Change-Id: I21db7d5bd86b98faaa1a1cd3f985daa592556a2d
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>

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Merge "feat(mt8188): add support for SMC from OP-TEE" into integration

fix(ti): fix TISCI API changes during refactor

The refactor caused many APIs to be regressed due to copy paste changes
so fix them.

Fixes: 6688fd7aec2f ("refactor(ti): refactor ti_sci_{setup,do}_xf

fix(ti): fix TISCI API changes during refactor

The refactor caused many APIs to be regressed due to copy paste changes
so fix them.

Fixes: 6688fd7aec2f ("refactor(ti): refactor ti_sci_{setup,do}_xfer to allow zero size response")
Change-Id: I03a808fa0bf2cbefbc1c9924bdaf4cfb2ad7f2cb
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>

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refactor(qemu): handle pointer authentication

Pointer authentication requires CTX_INCLUDE_PAUTH_REGS to be defined.

Change-Id: I4ca95d6d9e619e7a7296a2c3ecb799683bf70575
Signed-off-by: Marcin Juszki

refactor(qemu): handle pointer authentication

Pointer authentication requires CTX_INCLUDE_PAUTH_REGS to be defined.

Change-Id: I4ca95d6d9e619e7a7296a2c3ecb799683bf70575
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

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refactor(qemu): move options to start of file

There are some variables to enable/disable options. Let keep them at top
of file.

Change-Id: I108dd814557b6c713aba0d73a52148c766079c8b
Signed-off-by: M

refactor(qemu): move options to start of file

There are some variables to enable/disable options. Let keep them at top
of file.

Change-Id: I108dd814557b6c713aba0d73a52148c766079c8b
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

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refactor(qemu): keep AArch64 cpu flags in one section

There is no need to have two "if" checks for same thing one after
another.

FGT, RNG, SVE, SME are aarch64 only flags.

Change-Id: I6e5850211c85

refactor(qemu): keep AArch64 cpu flags in one section

There is no need to have two "if" checks for same thing one after
another.

FGT, RNG, SVE, SME are aarch64 only flags.

Change-Id: I6e5850211c859dc7a4ccf6bc8dc6a8d600ffe692
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

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refactor(qemu): handle SPM_MM builds

SPM_MM is not compatible with ENABLE_SVE_FOR_NS and breaks build early:

> Including SPM Management Mode (MM) makefile
> services/std_svc/spm/spm_mm/spm_mm.mk:14

refactor(qemu): handle SPM_MM builds

SPM_MM is not compatible with ENABLE_SVE_FOR_NS and breaks build early:

> Including SPM Management Mode (MM) makefile
> services/std_svc/spm/spm_mm/spm_mm.mk:14: *** "Error: SPM_MM is not compatible with ENABLE_SVE_FOR_NS". Stop.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: Iabe181647fce00a432ae11dc4599b71619364c24

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refactor(qemu): handle AArch64 flags

Handle coherency in one place for AArch64 mode.

Change-Id: Id3678a8f478e5ef731c81c0df30059000e380758
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linar

refactor(qemu): handle AArch64 flags

Handle coherency in one place for AArch64 mode.

Change-Id: Id3678a8f478e5ef731c81c0df30059000e380758
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

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