Merge "fix(fvp): adjust BL2 maximum size as per total SRAM size" into integration

fix(fvp): adjust BL2 maximum size as per total SRAM size

Adjusted BL2 maximum size as per total SRAM size.

Change-Id: Ic3b398574a17e8a784e7c4dbe3fe69d1fb2b5e16
Signed-off-by: Manish V Badarkhe <Man

fix(fvp): adjust BL2 maximum size as per total SRAM size

Adjusted BL2 maximum size as per total SRAM size.

Change-Id: Ic3b398574a17e8a784e7c4dbe3fe69d1fb2b5e16
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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feat(mte): adds feature detection for MTE_PERM

Adds feature detection for v8.9 feature FEAT_MTE_PERM. Adds respective
ID_AA64PFR2_EL1 definitions and ENABLE_FEAT_MTE_PERM define.

Change-Id: If24b42

feat(mte): adds feature detection for MTE_PERM

Adds feature detection for v8.9 feature FEAT_MTE_PERM. Adds respective
ID_AA64PFR2_EL1 definitions and ENABLE_FEAT_MTE_PERM define.

Change-Id: If24b42f1207154e639016b0b840b2d91c6ee13d4
Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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feat(msm8916): add port for MDM9607

The Qualcomm X5 Modem (MDM9607) SoC is very similar to the existing
MSM8916, except for:

- Single core ARM Cortex-A7
- No GPU
- MMU-500 r2p4 instead of r0p

feat(msm8916): add port for MDM9607

The Qualcomm X5 Modem (MDM9607) SoC is very similar to the existing
MSM8916, except for:

- Single core ARM Cortex-A7
- No GPU
- MMU-500 r2p4 instead of r0p0 (need to clear CACHE_LOCK bit)
- Different default BL31/BL33 address and UART number

Make the existing MSM8916 platform port usable for MDM9607 as well by
adding some minimal if statements where necessary plus the platform
make files for mdm9607.

Change-Id: I4dd02c8e29af6282d8d828c3027c5e333459ba36
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

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refactor(msm8916): handle single core platforms

Some Qualcomm modem platforms (MDM*) are quite similar to MSM8916
except that there is just a single CPU core. This requires some special
handling:

refactor(msm8916): handle single core platforms

Some Qualcomm modem platforms (MDM*) are quite similar to MSM8916
except that there is just a single CPU core. This requires some special
handling:

- There is no GPU so the GPU SMMU also does not exist.
- Looking closely at dumps of the MMIO register regions reveals that
some of the register addresses are slightly different.

Add the necessary checks for this to allow building for those
platforms.

No functional change for existing platforms.

Change-Id: I0380ac3734876243e970a55d8bec5a8247175343
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

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feat(msm8916): add port for MSM8939

The Qualcomm Snapdragon 615 (MSM8939) SoC is very similar to the
existing MSM8916, except for:

- Two clusters with ARM Cortex-A53 cores
- CCI-400

Make the e

feat(msm8916): add port for MSM8939

The Qualcomm Snapdragon 615 (MSM8939) SoC is very similar to the
existing MSM8916, except for:

- Two clusters with ARM Cortex-A53 cores
- CCI-400

Make the existing MSM8916 platform port usable for MSM8939 as well by
adding some minimal if statements where necessary plus the platform
make files for msm8939.

Change-Id: I8cda83dc642f62222f984a42eec14de5df4c11e3
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

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feat(msm8916): power on L2 caches for secondary clusters

On platforms with multiple CPU clusters the L2 cache will be only on
for the cluster of the boot CPU. Add the necessary sequence to power it

feat(msm8916): power on L2 caches for secondary clusters

On platforms with multiple CPU clusters the L2 cache will be only on
for the cluster of the boot CPU. Add the necessary sequence to power it
up for secondary clusters similar to the CPU boot sequence.

No functional change for platforms with a single cluster. The new code
is discarded entirely in this case.

Change-Id: I3d3bce519a8a10ef5278d74d81acf59123e00454
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

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feat(msm8916): initialize CCI-400 for multiple clusters

The MSM8939 SoC is very similar to MSM8916 but uses an ARM CCI-400
for cache coherence between the two CPU clusters. Add the necessary
code to

feat(msm8916): initialize CCI-400 for multiple clusters

The MSM8939 SoC is very similar to MSM8916 but uses an ARM CCI-400
for cache coherence between the two CPU clusters. Add the necessary
code to initialize it with the existing driver.

No functional change for platforms with a single cluster. The CCI
related code is discarded entirely in this case.

Change-Id: I041d60222d8d2aeca53b392934c87280c66b0db0
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

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refactor(msm8916): handle multiple CPU clusters

Some Qualcomm platforms similar to MSM8916 have multiple CPU clusters.
In this case, some of the hardware blocks are duplicated and must be
configured

refactor(msm8916): handle multiple CPU clusters

Some Qualcomm platforms similar to MSM8916 have multiple CPU clusters.
In this case, some of the hardware blocks are duplicated and must be
configured separately.

Refactor the code to handle additional clusters by introducing loops
and some conditionals.

No functional change for existing single cluster platforms.

Change-Id: I5b4b1ad2a1adde559d5b79b7698afe73733b2e90
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

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feat(msm8916): add port for MSM8909

The Qualcomm Snapdragon 210 (MSM8909) SoC is very similar to the
existing MSM8916, except for:

- ARM Cortex-A7 instead of Cortex-A53 (AArch32-only)
- MMU-500

feat(msm8916): add port for MSM8909

The Qualcomm Snapdragon 210 (MSM8909) SoC is very similar to the
existing MSM8916, except for:

- ARM Cortex-A7 instead of Cortex-A53 (AArch32-only)
- MMU-500 r2p0 instead of r0p0 (need to clear CACHE_LOCK bit)
- Different default BL31 address and UART number

Make the existing MSM8916 platform port usable for MSM8909 as well by
adding some minimal if statements where necessary plus the platform
make files for msm8909.

Change-Id: I8eca5bd8f2486cc2174562fb5de28f8dffa0d874
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

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feat(msm8916): clear CACHE_LOCK for MMU-500 r2p0+

Newer Qualcomm platforms similar to MSM8916 use MMU-500 r2p0+ instead
of MMU-500 r0p0. On these versions it is necessary to clear the
SMMU_sACR.CACH

feat(msm8916): clear CACHE_LOCK for MMU-500 r2p0+

Newer Qualcomm platforms similar to MSM8916 use MMU-500 r2p0+ instead
of MMU-500 r0p0. On these versions it is necessary to clear the
SMMU_sACR.CACHE_LOCK bit to allow the normal world to write to
SMMU_CBn_ACTLR. Without this Linux shows a warning and is unable to
workaround the errata in MMU-500:

arm-smmu 1e00000.iommu: Failed to disable prefetcher
[errata #841119 and #826419], check ACR.CACHE_LOCK

Handle this dynamically at runtime by enabling all the necessary SMMU
clocks and check the IDR7 register for MMU-500 r2p0+. This must be
applied to both SMMUs on the platform: APPS and GPU.

While at it clean up the clock handling: Leave the SMMU clocks on
because the normal world will need it again while booting. But make
sure the vote register of the RPM co-processor does not keep these
clocks always-on. For some reasons some platforms seem to have a
non-zero reset value for GCC_RPM_SMMU_CLOCK_BRANCH_ENA_VOTE.

Change-Id: I34cf7d3f2db977b0930eb6e64a870ecaf02a7573
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

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style(msm8916): add missing braces to while statements

According to the coding style all conditional statements (such as if,
for, while, do) must use braces regardless of the number of the
statement

style(msm8916): add missing braces to while statements

According to the coding style all conditional statements (such as if,
for, while, do) must use braces regardless of the number of the
statements in the body [1].

Fix this for the code inside plat/qti/msm8916.

[1]: https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-style.html#conditional-statement-bodies

Change-Id: I74f2e65aa2b3a65899e37dfd3f481d90fb15531c
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

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Merge "fix(spmd): perform G0 interrupt acknowledge and deactivation" into integration

Merge "refactor(tc): move all plat tests in test makefile" into integration

Merge changes from topics "rotpk_rss_interface", "rss_interfaces" into integration

* changes:
refactor(tc): print RSS interface test PSA status
test(tc): test for AP/RSS interface for ROTPK
fe

Merge changes from topics "rotpk_rss_interface", "rss_interfaces" into integration

* changes:
refactor(tc): print RSS interface test PSA status
test(tc): test for AP/RSS interface for ROTPK
feat(psa): interface with RSS for retrieving ROTPK

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refactor(tc): move all plat tests in test makefile

Moving all PLATFORM_TESTS into platform test makefile

Change-Id: I31821e9e69d916d12ae4c804df26f07fb523c835
Signed-off-by: Lauren Wehrmeister <laur

refactor(tc): move all plat tests in test makefile

Moving all PLATFORM_TESTS into platform test makefile

Change-Id: I31821e9e69d916d12ae4c804df26f07fb523c835
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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fix(spmd): perform G0 interrupt acknowledge and deactivation

Prior to delegating handling of Group0 secure interrupt to platform
handler, SPMD framework must acknowledge the highest pending interrup

fix(spmd): perform G0 interrupt acknowledge and deactivation

Prior to delegating handling of Group0 secure interrupt to platform
handler, SPMD framework must acknowledge the highest pending interrupt.
Moreover, once the platform has handled the interrupt successfully,
SPMD must deactivate the interrupt.

The rationale behind this decision is SPMD framework is well suited to
perform interrupt management at GIC boundary while the platform handler
is well equipped to deal with the device interface related to the
interrupt.

This patch also fixes a bug in the error code returned upon invocation
of FFA_EL3_INTR_HANDLE from normal world.

Change-Id: If8fef51899e25f966038cc01ec58c84ee25e88eb
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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refactor(tc): print RSS interface test PSA status

Adding PSA status to print statement upon failing communication
initialization, non-volatile counter, and rotpk read interface calls in
platform_tes

refactor(tc): print RSS interface test PSA status

Adding PSA status to print statement upon failing communication
initialization, non-volatile counter, and rotpk read interface calls in
platform_tests.

Change-Id: Ia949cc2d18e93efb68f663d0c4e5500ca9021a94
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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test(tc): test for AP/RSS interface for ROTPK

Adding new test for AP/RSS interface for reading ROTPK for
each 3 types of ROTPKs for: CCA, secure, and non-secure firmware.

Enabled by PLATFORM_TEST=r

test(tc): test for AP/RSS interface for ROTPK

Adding new test for AP/RSS interface for reading ROTPK for
each 3 types of ROTPKs for: CCA, secure, and non-secure firmware.

Enabled by PLATFORM_TEST=rss-rotpk.

Update to print output when AP/RSS interface platform tests
pass to be able to reuse expect script functionality in CI.

Change-Id: Icc50b090e18a272378751fda104d209738b5b70c
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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Merge "feat(mt8188): modify APU DAPC permission" into integration

Merge changes from topic "xlnx_dtb_modification" into integration

* changes:
feat(versal-net): ddr address reservation in dtb at runtime
feat(versal): ddr address reservation in dtb at runtime

feat(mt8188): modify APU DAPC permission

We limited the r/w permission of some register groups for security
concerns. These regitser groups should not be accessed by domain 3 or
domain 5.

Change-Id

feat(mt8188): modify APU DAPC permission

We limited the r/w permission of some register groups for security
concerns. These regitser groups should not be accessed by domain 3 or
domain 5.

Change-Id: I2188da88d9e10a931d87bda14dc7dca46633dcd8
Signed-off-by: Chungying Lu <chungying.lu@mediatek.corp-partner.google.com>

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Merge "build(fpga): remove a710 from fpga build" into integration

Merge changes from topic "master" into integration

* changes:
fix(tc): rename macro to match PSA spec
fix(tc): Correct return type

feat(versal-net): ddr address reservation in dtb at runtime

When the TF-A is placed in DDR memory range, the DDR memory range
needs to be explicitly reserved in the default device tree.

A new build

feat(versal-net): ddr address reservation in dtb at runtime

When the TF-A is placed in DDR memory range, the DDR memory range
needs to be explicitly reserved in the default device tree.

A new build time parameter, XILINX_OF_BOARD_DTB_ADDR, is introduced.
The TF-A will reserve the DDR memory only when a valid DTB address
is provided to XILINX_OF_BOARD_DTB_ADDR during build.

Now the user has options, either manually reserve the desired DDR
address range for TF-A in device tree or let TF-A access and modify
the device tree, to reserve the DDR address range, in runtime using
the build parameter.

Change-Id: I45a5d9a8343ea8a19ea014a70023731de94d061a
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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