fix(st): update dt_get_ddr_size() type

Move to size_t to ensure a generic algorithm whatever the platform
architecture.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I7879367

fix(st): update dt_get_ddr_size() type

Move to size_t to ensure a generic algorithm whatever the platform
architecture.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I7879367849ed86750dcff2b6a15f4b998bf6da18
Signed-off-by: Sebastien PASDELOUP <sebastien.pasdeloup-ext@st.com>

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feat(xilinx): sync macro names

There is no reason to have platform specific macros where generic
macros can be used. This is pretty much preparation step for moving
console code to single location w

feat(xilinx): sync macro names

There is no reason to have platform specific macros where generic
macros can be used. This is pretty much preparation step for moving
console code to single location where multiple combinations can be
easier to handle.

Change-Id: I4d85ddef29f5870a9ea9590d4d1564469c6eb87e
Signed-off-by: Michal Simek <michal.simek@amd.com>

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feat(xilinx): remove crash console unused macros

Macros are not used that's why remove them.

Change-Id: I4519ea0b9e30b757ab8a6ee3bb56af45dddc0d96
Signed-off-by: Michal Simek <michal.simek@amd.com>

Merge changes from topic "xilinx-crash" into integration

* changes:
feat(xilinx): used console also as crash console
feat(versal-net): remove empty crash console setup

feat(mt8188): update return value in mtk_emi_mpu_sip_handler

Remove the use of SMC_RET2 in the mtk_emi_mpu_sip_handler function. The
current smc driver in the atf driver has switched to using SMC_RE

feat(mt8188): update return value in mtk_emi_mpu_sip_handler

Remove the use of SMC_RET2 in the mtk_emi_mpu_sip_handler function. The
current smc driver in the atf driver has switched to using SMC_RET4 for
smc call clients. This change aligns the return value handling with the
updated driver behavior that ensures consistency and avoids potential
issues with the old return value.

Change-Id: I87f25b438d2119837c45bed80a8224fcfd141fb6
Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>
Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com>

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Merge "fix(corstone-1000): add cpu_helpers.S to platform.mk" into integration

refactor(el3-runtime): plat_ic_has_interrupt_type returns bool

Rather than returning 0 or 1, the above function returns bool false
or true. No functional change.

Change-Id: Iea904ffc368568208fa8203

refactor(el3-runtime): plat_ic_has_interrupt_type returns bool

Rather than returning 0 or 1, the above function returns bool false
or true. No functional change.

Change-Id: Iea904ffc368568208fa8203e0d2e0cdaa500b1e0
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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fix(el3-runtime): leverage generic interrupt controller helpers

Rather than validating the type of interrupts supported by the
platform interrupt controller, the interrupt management framework can
d

fix(el3-runtime): leverage generic interrupt controller helpers

Rather than validating the type of interrupts supported by the
platform interrupt controller, the interrupt management framework can
directly use helper utilities implemented by the generic interrupt
controller driver.

Change-Id: I735f8d2742a2c7974d11c0a5ddc771ad807c635c
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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fix(gicv3): map generic interrupt type to GICv3 group

The generic interrupt controller identifies an interrupt based on its
type whereas the GIC uses the notion of groups to identify an
interrupt.

fix(gicv3): map generic interrupt type to GICv3 group

The generic interrupt controller identifies an interrupt based on its
type whereas the GIC uses the notion of groups to identify an
interrupt.

Currently, they are used interchangeably in GICv3 driver. It did not
cause any functional issues since the matching type and group had the
same value for corresponding macros. This patch makes the necessary
fixes.

The generic interrupt controller APIs, such as
plat_ic_set_interrupt_type map interrupt type to interrupt group
supported by the GICv3 IP. Similarly, other generic interrupt
controller APIs map interrupt group to interrupt type as needed.

This patch also changes the name of the helper functions to use group
rather than type for handling interrupts.

Change-Id: Ie2d88a3260c71e4ab9c8baacde24cc21e551de3d
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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chore(gicv2): use interrupt group instead of type

The generic interrupt controller identifies an interrupt based on its
type whereas the GIC uses the notion of groups to identify an
interrupt.

This

chore(gicv2): use interrupt group instead of type

The generic interrupt controller identifies an interrupt based on its
type whereas the GIC uses the notion of groups to identify an
interrupt.

This patch changes the name of the helper functions to use group
rather than type for handling interrupts. No functional change in this
patch.

Change-Id: If13ec65cc6c87c2da73a3d54b033f02635ff924a
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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fix(spmd): coverity scan issues

Coverity defects fixed by this patch are:
*** CID 400208: Performance inefficiencies (PASS_BY_VALUE)
/include/services/el3_spmd_logical_sp.h: 108 in
ffa_partition_i

fix(spmd): coverity scan issues

Coverity defects fixed by this patch are:
*** CID 400208: Performance inefficiencies (PASS_BY_VALUE)
/include/services/el3_spmd_logical_sp.h: 108 in
ffa_partition_info_regs_get_last_idx()

*** CID 400207: Performance inefficiencies (PASS_BY_VALUE)
/services/std_svc/spmd/spmd_logical_sp.c: 359 in
ffa_partition_info_regs_get_part_info()

Signed-off-by: Raghu Krishnamurthy <raghu.ncstate@gmail.com>
Change-Id: I9597377a8ec3d5519995e1619d99ee7102f33939

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feat(xilinx): used console also as crash console

CONSOLE_FLAG_CRASH should be also setup to get crash logs on
the same console. Both platforms are using crash console
implementation from plat/common

feat(xilinx): used console also as crash console

CONSOLE_FLAG_CRASH should be also setup to get crash logs on
the same console. Both platforms are using crash console
implementation from plat/common/aarch64/crash_console_helpers.S
that's why there is necessary to setup CONSOLE_FLAG_CRASH.
plat_crash_console_putc() implementation is saying:
"int plat_crash_console_putc(char c)
Prints the character on all consoles registered with the console
framework that have CONSOLE_FLAG_CRASH set. Note that this is only
helpful for crashes that occur after the platform intialization code
has registered a console. Platforms using this implementation need to
ensure that all console drivers they use that have the CRASH flag set
support this (i.e. are written in assembly and comply to the register
clobber requirements of plat_crash_console_putc()."

Change-Id: I314cacbcb0bfcc85fe734882e38718f2763cdbf4
Signed-off-by: Michal Simek <michal.simek@amd.com>

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feat(versal-net): remove empty crash console setup

Private plat_crash_console_init() has all the setup commented
that's why it was never been tested.
pl011 uart is supposed to be used as crash conso

feat(versal-net): remove empty crash console setup

Private plat_crash_console_init() has all the setup commented
that's why it was never been tested.
pl011 uart is supposed to be used as crash console and it should be
enought to add CONSOLE_FLAG_CRASH and remove platform specific
implementation and use generic one.
Early console can't be used for early ASM debugging but that's
expected and not required.

Change-Id: I1267fd78c0d6532a0baddbcad8a5b2a7dfc7750b
Signed-off-by: Michal Simek <michal.simek@amd.com>

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Merge "chore: remove MULTI_CONSOLE_API references" into integration

Merge "fix(qemu_sbsa): align FIP base to BL1 size" into integration

fix(qemu_sbsa): align FIP base to BL1 size

RME patch series shown that we can build larger BL1 than we can run:

NOTICE: Booting Trusted Firmware
NOTICE: BL1: v2.9(debug):v2.9.0-736-g08548888a
NOT

fix(qemu_sbsa): align FIP base to BL1 size

RME patch series shown that we can build larger BL1 than we can run:

NOTICE: Booting Trusted Firmware
NOTICE: BL1: v2.9(debug):v2.9.0-736-g08548888a
NOTICE: BL1: Built : 12:10:39, Sep 18 2023
INFO: BL1: RAM 0x3ffee000 - 0x3fffb000
INFO: BL1: Loading BL2
WARNING: Firmware Image Package header check failed.

RME pushed debug build BL1 over 0x8000 in size.
This exposed an error where FIP_BASE (supposed to be at BL1_SIZE offset
from start of flash) was actually 0x8000 and not 0x12000.
Make sure we have space for BL1 by deriving FIP_BASE from it.

Note: this is a breaking change for edk2 FD image generation, which had
similarly hardcoded a 0x8000 offset. These images must be updated in
lock-step.

Change-Id: I8a1a85e82319945a4412c424467d818d5b6e4ecd
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

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feat(qemu): add "neoverse-n2" cpu support

Add support to qemu "neoverse-n2" cpu for "qemu" platform.
This one has 2^48 address space so will be used by both systems.

Signed-off-by: Marcin Juszkiewi

feat(qemu): add "neoverse-n2" cpu support

Add support to qemu "neoverse-n2" cpu for "qemu" platform.
This one has 2^48 address space so will be used by both systems.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I9f0fa23a4934d9464379495225e08adc121325b4

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Merge changes from topic "stm32mp2" into integration

* changes:
feat(stm32mp2): generate stm32 file
feat(stm32mp2-fdts): add stm32mp257f-ev1 board
feat(stm32mp2-fdts): introduce stm32mp25 pinc

Merge changes from topic "stm32mp2" into integration

* changes:
feat(stm32mp2): generate stm32 file
feat(stm32mp2-fdts): add stm32mp257f-ev1 board
feat(stm32mp2-fdts): introduce stm32mp25 pinctrl files
feat(stm32mp2-fdts): introduce stm32mp25 SoCs family
feat(stm32mp2): add console configuration
feat(st): add RCC registers list
feat(st-uart): add AARCH64 stm32_console driver
feat(st): introduce new platform STM32MP2
feat(dt-bindings): add the STM32MP2 clock and reset bindings
docs(changelog): add scopes for STM32MP2
feat(docs): introduce STM32MP2 doc
refactor(docs): add a sub-menu for ST platforms
refactor(st): move plat_image_load.c
refactor(st): rename PLAT_NB_FIXED_REGS
refactor(st): move some storage definitions to common part
refactor(st): move SDMMC definitions to driver
feat(st-clock): stub fdt_get_rcc_secure_state
feat(st-clock): allow aarch64 compilation of STGEN functions
feat(st): allow AARCH64 compilation for common code
refactor(st): rename QSPI macros

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Merge changes from topic "xlnx_mmap_dynamic_dtb" into integration

* changes:
fix(xilinx): dcache flush for dtb region
fix(xilinx): dynamic mmap region for dtb

Merge "feat(qemu): add A55 cpu support for virt" into integration

Merge "fix(plat/arm): do not program DSU CLUSTERPWRDN register" into integration

fix(plat/arm): do not program DSU CLUSTERPWRDN register

This reverts commit 9cf7f355ce8984a4cde970d5f57c913d5247ca6d.

Above mentioned commit was writing to cluster power required bit of
CLUSTERPWRD

fix(plat/arm): do not program DSU CLUSTERPWRDN register

This reverts commit 9cf7f355ce8984a4cde970d5f57c913d5247ca6d.

Above mentioned commit was writing to cluster power required bit of
CLUSTERPWRDN register, which provides an advisory status to the power
controller.
Bit definition indication:
0 : Cluster power is not required when all cores are powered down
1 : Cluster power is required even when all cores are powered down
RESET value of this bit is 0

The current implementation in TF-A just programs this bit to 0 when
cluster power down is done but it never sets it to 1. Which actully
does not change any behaviour as the value of this bit always remains 0.

Ideally this bit has to be set to 1 when a core powers up (as RESET
value is 0) and set it to 0 for any core power down except if its last
man standing, in that case we need to ensure the target power level
from OS is cluster then we can do set it to 0.
There also are some investigation needs to be done to find that whether
we need a explicit message to power controller for turning cluster OFF
or it will happen automatically.

Considering this needs a bit of analysis as well as a platform to test
it on, revert the changes which impact the programming during cluster
power down and just keep register defnition.

Change-Id: I4c4ebedae7ca9cd081fb1e0605b9d906d77614d9
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>

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Merge "fix(fvp): conditionally increase XLAT and MMAP table entries" into integration

fix(xilinx): dcache flush for dtb region

flush dcache region for dtb so that dtb cache entries are first written
to disk and are invalidated afterwards to avoid presence of any stale
dtb related ent

fix(xilinx): dcache flush for dtb region

flush dcache region for dtb so that dtb cache entries are first written
to disk and are invalidated afterwards to avoid presence of any stale
dtb related entry in the dcache.

Change-Id: Ide0ed58f799b35b690ed790c7498ecdc334e02f5
Signed-off-by: Amit Nagal <amit.nagal@amd.com>

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fix(xilinx): dynamic mmap region for dtb

mmap dtb region before usage and unmap it after usage.
overall size(text,data,bss) of dtb gets reduced by
16 bytes in normal flow and 80 bytes in ddr flow.

fix(xilinx): dynamic mmap region for dtb

mmap dtb region before usage and unmap it after usage.
overall size(text,data,bss) of dtb gets reduced by
16 bytes in normal flow and 80 bytes in ddr flow.

Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Change-Id: I411deff57ab141fc2978a2e916aec2d988cb8f9c

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