Merge changes I9c2bf78a,Iaff5f1fa,I44686a36 into integration

* changes:
fix(imx8m): map BL32 memory only if SPD_opteed or SPD_trusty is enabled
feat(imx8mn): add workaround for errata ERR050362

Merge changes I9c2bf78a,Iaff5f1fa,I44686a36 into integration

* changes:
fix(imx8m): map BL32 memory only if SPD_opteed or SPD_trusty is enabled
feat(imx8mn): add workaround for errata ERR050362
feat(imx8m): enable snvs privileged registers access

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refactor(zynqmp): use common code for prepare_dtb

use common code definition and remove zynqmp local definition
for prepare_dtb in dtb flows.

Change-Id: I362b90b96852e9afccc8a2e23d3b7f709280fba7
Si

refactor(zynqmp): use common code for prepare_dtb

use common code definition and remove zynqmp local definition
for prepare_dtb in dtb flows.

Change-Id: I362b90b96852e9afccc8a2e23d3b7f709280fba7
Signed-off-by: Amit Nagal <amit.nagal@amd.com>

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refactor(xilinx): remove multiple return paths in prepare_dtb

presence of multiple return path in prepare_dtb results in misra c
violation 15.5: this return statement is not the final statement
in t

refactor(xilinx): remove multiple return paths in prepare_dtb

presence of multiple return path in prepare_dtb results in misra c
violation 15.5: this return statement is not the final statement
in the compound statement that forms the body of the function.
prepare_dtb is refactored to address the same.

Change-Id: I17ca4314202d6ca8d6fb0c4ea2ed9d31a152371b
Signed-off-by: Amit Nagal <amit.nagal@amd.com>

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fix(imx8m): map BL32 memory only if SPD_opteed or SPD_trusty is enabled

Always map the BL32 memory can interfere with the BL33 mapping if the
BL33 is not aware of the mapping, e.g. different memory

fix(imx8m): map BL32 memory only if SPD_opteed or SPD_trusty is enabled

Always map the BL32 memory can interfere with the BL33 mapping if the
BL33 is not aware of the mapping, e.g. different memory tagging
secure/non-secure. Therefore map the memory only if BL32 (opteed,
trusty) is enabled and BL33 is aware of this memory mapping.

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Change-Id: I9c2bf78aa6e88c93e749a9248724186fee9df864

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feat(imx8mn): add workaround for errata ERR050362

Port the workaround from the downstream imx-atf [1]:

| commit 1990081264f40822d1564f4562f05bbbc0c2941b
| Author: Ji Luo <ji.luo@nxp.com>
| Date:

feat(imx8mn): add workaround for errata ERR050362

Port the workaround from the downstream imx-atf [1]:

| commit 1990081264f40822d1564f4562f05bbbc0c2941b
| Author: Ji Luo <ji.luo@nxp.com>
| Date: Thu May 20 16:26:55 2021 +0800
|
| MA-19071 imx8mn: workaround for errata ERR050362
|
| Configure the force_incr programmable bit in GPV_5 of PL301_display,
| which fixes partial write issue. This workaround was done in MCU FW
| before, move it to TF-A now as MCU should not touch secure world.
|
| Change-Id: I2e5bbc764640afeab6ac2f4b202939b59bd3b3f2
| Signed-off-by: Ji Luo <ji.luo@nxp.com>

[1] https://github.com/nxp-imx/imx-atf.git

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Change-Id: Iaff5f1faa143204d64c075b288f8dd13eb2902d8

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feat(imx8m): enable snvs privileged registers access

Allow non-privileged access to all SNVS registers in case of no TEE is
available.

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Change-I

feat(imx8m): enable snvs privileged registers access

Allow non-privileged access to all SNVS registers in case of no TEE is
available.

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Change-Id: I44686a3639a68c72c7eacc80691c294d5c32c9ae

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fix(versal-net): use correct macro name for uart baudrate

Address an issue where incorrect macro name is being used for
setting the UART buad rate. Updated the code to use the
appropriate macro name

fix(versal-net): use correct macro name for uart baudrate

Address an issue where incorrect macro name is being used for
setting the UART buad rate. Updated the code to use the
appropriate macro name, ensuring that baud rate name is proper.

Fixes: 04a483359fef ("feat(xilinx): sync macro names")
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: I27dd8b1559beb0cf7b872de037adc95a948ecc2f

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Merge changes from topic "st_fixes" into integration

* changes:
fix(st): enable RTC clock before accessing nv counter
fix(st-crypto): use GENMASK_32 to define PKA registers masks
fix(st): upda

Merge changes from topic "st_fixes" into integration

* changes:
fix(st): enable RTC clock before accessing nv counter
fix(st-crypto): use GENMASK_32 to define PKA registers masks
fix(st): update comment on encryption key
fix(st): allow crypto lib compilation in aarch64
fix(st-uart): allow 64 bit compilation
fix(st): reduce MMC block_buffer
fix(stm32mp13-fdts): cosmetic fixes in PLL nodes
fix(st): update dt_get_ddr_size() type
fix(nand): reset the SLC NAND
fix(st-crypto): do not read RNG data if it's not ready

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Merge "feat(mt8188): add DSB before udelay" into integration

Merge "feat(rmmd): enable SME for RMM" into integration

Merge changes from topic "xilinx-console-sync" into integration

* changes:
fix(xilinx): remove console error message
feat(xilinx): sync macro names
feat(xilinx): remove crash console unused ma

Merge changes from topic "xilinx-console-sync" into integration

* changes:
fix(xilinx): remove console error message
feat(xilinx): sync macro names
feat(xilinx): remove crash console unused macros

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feat(mt8188): add DSB before udelay

To ensure that all explicit memory accesses are complete before udelay,
insert dsb before udelay.

Change-Id: If119e920e29539ae8b68d3c44c8f77b5bf424a1a
Signed-off

feat(mt8188): add DSB before udelay

To ensure that all explicit memory accesses are complete before udelay,
insert dsb before udelay.

Change-Id: If119e920e29539ae8b68d3c44c8f77b5bf424a1a
Signed-off-by: Karl Li <karl.li@mediatek.com>

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feat(rmmd): enable SME for RMM

This patch enables Scalable Matrix Extension (SME) for RMM. RMM will
save/restore required registers that are shared with SVE/FPU register
state so that Realm can use

feat(rmmd): enable SME for RMM

This patch enables Scalable Matrix Extension (SME) for RMM. RMM will
save/restore required registers that are shared with SVE/FPU register
state so that Realm can use FPU or SVE.

The Relevant RMM support can be found here :
https://github.com/TF-RMM/tf-rmm/commit/0ccd7ae58b00

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: I3bbdb840e7736dec00b71c85fcec3d5719413ffd

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Merge changes from topic "rm/handoff" into integration

* changes:
feat(qemu): implement firmware handoff on qemu
feat(handoff): introduce firmware handoff library

fix(xilinx): remove console error message

If console is not found there is no way where to print information about
it. Currently only cdns/dcc/pl011 uarts are supported that's why remove
the message

fix(xilinx): remove console error message

If console is not found there is no way where to print information about
it. Currently only cdns/dcc/pl011 uarts are supported that's why remove
the message which none can see anyway.
But keep "else" part with comment to avoid misra c rule 15.7 violation
which is also missing in Versal NET implementation.

Change-Id: I78e3baffd2288d2a4673099bf193f22029912840
Signed-off-by: Michal Simek <michal.simek@amd.com>

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Merge "refactor(ast2700): adopt RESET_TO_BL31 boot flow" into integration

Merge changes from topic "mp/fix_interrupt_type" into integration

* changes:
refactor(el3-runtime): plat_ic_has_interrupt_type returns bool
fix(el3-runtime): leverage generic interrupt controlle

Merge changes from topic "mp/fix_interrupt_type" into integration

* changes:
refactor(el3-runtime): plat_ic_has_interrupt_type returns bool
fix(el3-runtime): leverage generic interrupt controller helpers
fix(gicv3): map generic interrupt type to GICv3 group
chore(gicv2): use interrupt group instead of type

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refactor(ast2700): adopt RESET_TO_BL31 boot flow

Revise the AST2700 boot flow to the RESET_TO_BL31 scheme.
The execution of BL1/2 can be saved from ARM CA35 while most
low level platform initializat

refactor(ast2700): adopt RESET_TO_BL31 boot flow

Revise the AST2700 boot flow to the RESET_TO_BL31 scheme.
The execution of BL1/2 can be saved from ARM CA35 while most
low level platform initialization are moved to a preceding MCU.

This patch updates the build configuration and also adds
the SMP mailbox setup code to hold secondary cores until
they are being waken up.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Change-Id: I7e0aa6416b92b97036153db1d9a26baaa41b7b18

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feat(qemu): implement firmware handoff on qemu

Implement firmware handoff from BL2 to BL33 on qemu platform
compliant to Firmware handoff specification v0.9.

Change-Id: Id8d5206a71ef6ec97cf3c97995d

feat(qemu): implement firmware handoff on qemu

Implement firmware handoff from BL2 to BL33 on qemu platform
compliant to Firmware handoff specification v0.9.

Change-Id: Id8d5206a71ef6ec97cf3c97995de328ebf0600cc
Signed-off-by: Raymond Mao <raymond.mao@linaro.org>

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fix(st): enable RTC clock before accessing nv counter

The plat_get_nv_ctr() retrieves the non-volatile counter value from
TAMP_COUNTR register in RTCTAMP peripheral. The clock needs to be
enabled be

fix(st): enable RTC clock before accessing nv counter

The plat_get_nv_ctr() retrieves the non-volatile counter value from
TAMP_COUNTR register in RTCTAMP peripheral. The clock needs to be
enabled before accessing it.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I2e9fc2c7ac516d6f8624cc6c9d442ee85629bf9a

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fix(st): update comment on encryption key

On STM32MP2, the encryption key is 32 bytes, the key duplication
(done for 16 bytes OTP) is not done. Update the comment to precise that.

Change-Id: I6fc4d

fix(st): update comment on encryption key

On STM32MP2, the encryption key is 32 bytes, the key duplication
(done for 16 bytes OTP) is not done. Update the comment to precise that.

Change-Id: I6fc4d652fdd462808918e85f6e5bd0d68d10d436
Yann Gautier <yann.gautier@foss.st.com>

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Merge "fix(spmd): coverity scan issues" into integration

fix(st): allow crypto lib compilation in aarch64

Cast len with size_t, as it is unsigned long on Aarch64, and no more
unsigned int. Changing functions prototypes will not help as
.verify_signature a

fix(st): allow crypto lib compilation in aarch64

Cast len with size_t, as it is unsigned long on Aarch64, and no more
unsigned int. Changing functions prototypes will not help as
.verify_signature awaits an unsigned int for its last parameter.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I9332fd46301a9653af917802788fd97fe7c8a162

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fix(st-uart): allow 64 bit compilation

Change a %x in %zx to print a size_t variable.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I27ac3739f4a2ec3b33c34d2257fa858cbd1aae6a

fix(st): reduce MMC block_buffer

This buffer used by io_block should be the size on one block (512 bytes)
not 512*4 due to the use of uint32_t. Change that to uint8_t. This
reduces the size of BSS b

fix(st): reduce MMC block_buffer

This buffer used by io_block should be the size on one block (512 bytes)
not 512*4 due to the use of uint32_t. Change that to uint8_t. This
reduces the size of BSS by 1.5KiB.

Change-Id: I8492f13f5386679b0c81efba66911422412782f9
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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