fix(xilinx): update dtb when dtb address and tf-a ddr flow is used

Memory reservation in dtb will be done only when TF-A runs from
ddr and dtb load address is provided.
Otherwise prepare_dtb will si

fix(xilinx): update dtb when dtb address and tf-a ddr flow is used

Memory reservation in dtb will be done only when TF-A runs from
ddr and dtb load address is provided.
Otherwise prepare_dtb will simply return.
Empty definition of prepare_dtb is removed.

Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Change-Id: Ie8a3ec51d60a7389831cfe6a112f722777930623

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fix(versal): use correct macro name for ocm base address

In absence of definition, PLAT_OCM_BASE is always 0
and IS_TFA_IN_OCM(x) always returns true irrespective
of address passed to it. Reasoning

fix(versal): use correct macro name for ocm base address

In absence of definition, PLAT_OCM_BASE is always 0
and IS_TFA_IN_OCM(x) always returns true irrespective
of address passed to it. Reasoning is as mentioned in
Refer section 4.2.3 in
https://gcc.gnu.org/onlinedocs/gcc-3.0.2/cpp_4.html
Due to this,functionality for reservation of TF-A DDR memory in
dtb is never executed.

Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Change-Id: Iafb6b7c6aec29bba22f8f7a8395f9caf97548157

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refactor(arm): avoid setting HASH_PREREQUISITES for a build without ROT_KEY

In the absence of ROT_KEY option, there is no need to populate
HASH_PREREQUISITES as the build system uses the hash file s

refactor(arm): avoid setting HASH_PREREQUISITES for a build without ROT_KEY

In the absence of ROT_KEY option, there is no need to populate
HASH_PREREQUISITES as the build system uses the hash file specified by
ARM_ROTPK_HASH directly.

Change-Id: Ib08f53b182b8446bbc430f2608471c7dfdc0e58c
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge "refactor(ast2700): update memory layout" into integration

refactor(ast2700): update memory layout

Update the memory layout for both BL31 and BL32 FW based on
the 1GB DRAM space of the AST2700 EVB.

Minor:
- Use SZ_xx macro to define size for better readab

refactor(ast2700): update memory layout

Update the memory layout for both BL31 and BL32 FW based on
the 1GB DRAM space of the AST2700 EVB.

Minor:
- Use SZ_xx macro to define size for better readability

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Change-Id: I6d8285bd675321f615bb67cdd27bb4b6cb4c8b16

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Merge "feat(cpus): add support for Nevis CPU" into integration

feat(cpus): add support for Nevis CPU

Adding basic CPU library code to support Nevis CPU

Change-Id: I399cc9b7b2d907b02b76ea2a3e5abb54e28fbf6c
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.co

feat(cpus): add support for Nevis CPU

Adding basic CPU library code to support Nevis CPU

Change-Id: I399cc9b7b2d907b02b76ea2a3e5abb54e28fbf6c
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>

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chore(npcm845x): remove pauth_helpers.S additions in platform makefile

Currently 'pauth_helpers.S' is added if pauth is enabled from main
level makefile.

Change-Id: I33800e280daea6dba6d11e2c494101b

chore(npcm845x): remove pauth_helpers.S additions in platform makefile

Currently 'pauth_helpers.S' is added if pauth is enabled from main
level makefile.

Change-Id: I33800e280daea6dba6d11e2c494101b369cd8a0b
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge "fix(nuvoton): fix typo in platform.mk" into integration

Merge "build(bl32): added check for AARCH32_SP" into integration

build(bl32): added check for AARCH32_SP

If AACRH32_SP is not specified, it causes the DEFAULT_LINKER_SCRIPT
variable to be empty, and then the linker takes the variable following
it as if it was the

build(bl32): added check for AARCH32_SP

If AACRH32_SP is not specified, it causes the DEFAULT_LINKER_SCRIPT
variable to be empty, and then the linker takes the variable following
it as if it was the linker script, which is not one. This patch
addresses that issue by requiring the AARCH32_SP variable to be set
before continuing.

Change-Id: I21db7d5bd86b98faaa1a1cd3f985daa592556a2d
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>

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Merge "feat(mt8188): add support for SMC from OP-TEE" into integration

fix(ti): fix TISCI API changes during refactor

The refactor caused many APIs to be regressed due to copy paste changes
so fix them.

Fixes: 6688fd7aec2f ("refactor(ti): refactor ti_sci_{setup,do}_xf

fix(ti): fix TISCI API changes during refactor

The refactor caused many APIs to be regressed due to copy paste changes
so fix them.

Fixes: 6688fd7aec2f ("refactor(ti): refactor ti_sci_{setup,do}_xfer to allow zero size response")
Change-Id: I03a808fa0bf2cbefbc1c9924bdaf4cfb2ad7f2cb
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>

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refactor(qemu): handle pointer authentication

Pointer authentication requires CTX_INCLUDE_PAUTH_REGS to be defined.

Change-Id: I4ca95d6d9e619e7a7296a2c3ecb799683bf70575
Signed-off-by: Marcin Juszki

refactor(qemu): handle pointer authentication

Pointer authentication requires CTX_INCLUDE_PAUTH_REGS to be defined.

Change-Id: I4ca95d6d9e619e7a7296a2c3ecb799683bf70575
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

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refactor(qemu): move options to start of file

There are some variables to enable/disable options. Let keep them at top
of file.

Change-Id: I108dd814557b6c713aba0d73a52148c766079c8b
Signed-off-by: M

refactor(qemu): move options to start of file

There are some variables to enable/disable options. Let keep them at top
of file.

Change-Id: I108dd814557b6c713aba0d73a52148c766079c8b
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

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refactor(qemu): keep AArch64 cpu flags in one section

There is no need to have two "if" checks for same thing one after
another.

FGT, RNG, SVE, SME are aarch64 only flags.

Change-Id: I6e5850211c85

refactor(qemu): keep AArch64 cpu flags in one section

There is no need to have two "if" checks for same thing one after
another.

FGT, RNG, SVE, SME are aarch64 only flags.

Change-Id: I6e5850211c859dc7a4ccf6bc8dc6a8d600ffe692
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

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refactor(qemu): handle SPM_MM builds

SPM_MM is not compatible with ENABLE_SVE_FOR_NS and breaks build early:

> Including SPM Management Mode (MM) makefile
> services/std_svc/spm/spm_mm/spm_mm.mk:14

refactor(qemu): handle SPM_MM builds

SPM_MM is not compatible with ENABLE_SVE_FOR_NS and breaks build early:

> Including SPM Management Mode (MM) makefile
> services/std_svc/spm/spm_mm/spm_mm.mk:14: *** "Error: SPM_MM is not compatible with ENABLE_SVE_FOR_NS". Stop.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: Iabe181647fce00a432ae11dc4599b71619364c24

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refactor(qemu): handle AArch64 flags

Handle coherency in one place for AArch64 mode.

Change-Id: Id3678a8f478e5ef731c81c0df30059000e380758
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linar

refactor(qemu): handle AArch64 flags

Handle coherency in one place for AArch64 mode.

Change-Id: Id3678a8f478e5ef731c81c0df30059000e380758
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

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refactor(qemu): common cpu features enablement

Enable SVE, SME, RNG, FGT in one place.

qemu gains FGT (needed for 'max' cpu to boot Linux)
qemu_sbsa gains RNG

Signed-off-by: Marcin Juszkiewicz <ma

refactor(qemu): common cpu features enablement

Enable SVE, SME, RNG, FGT in one place.

qemu gains FGT (needed for 'max' cpu to boot Linux)
qemu_sbsa gains RNG

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I2e8f971ef3e42d9ebe9f20641b288cc8c40f806a

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refactor(qemu): common BL31 sources

Move BL31 source list into common file.

Change-Id: Iaa27cfd8f87b691728379c87a6ff6331e87951e1
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

refactor(qemu): common BL1/2 sources

Move BL1 and BL2 source list into common file.

Change-Id: I8f9a835f6cd1c5d67728a071860173f80f03c84e
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro

refactor(qemu): common BL1/2 sources

Move BL1 and BL2 source list into common file.

Change-Id: I8f9a835f6cd1c5d67728a071860173f80f03c84e
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

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refactor(qemu): move CPU definitions into one place

Keep list of supported cpu cores in one place for both platforms.
qemu_sbsa does not handle some of them but with 256MB firmware space it
does not

refactor(qemu): move CPU definitions into one place

Keep list of supported cpu cores in one place for both platforms.
qemu_sbsa does not handle some of them but with 256MB firmware space it
does not matter.

Change-Id: I5b8f7d18dc903e86e0cc7babbc2fb3f26a1bfdfa
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

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refactor(qemu): move FDT stuff into one place

Move libfdt includes into common file and use definitions from them.

Change-Id: Ic4fe784fdbedcf5e9e3804a633fcac68464f38a6
Signed-off-by: Marcin Juszkie

refactor(qemu): move FDT stuff into one place

Move libfdt includes into common file and use definitions from them.

Change-Id: Ic4fe784fdbedcf5e9e3804a633fcac68464f38a6
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

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fix(nuvoton): fix typo in platform.mk

Fix typo of SPMD_SPM_AT_SEL2 in platform.mk

Signed-off-by: Margarita Glushkin <rutigl@gmail.com>
Change-Id: I06cfe2f1f0783edff513d83fef08eeed5f4fc58b

fix(scmi): add parameter for plat_scmi_clock_rates_array

Pass "start_idx" to plat_scmi_clock_rates_array.
This parameter is required to obtain the rate table
a second time.

Signed-off-by: XiaoDong

fix(scmi): add parameter for plat_scmi_clock_rates_array

Pass "start_idx" to plat_scmi_clock_rates_array.
This parameter is required to obtain the rate table
a second time.

Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
Change-Id: I97c6751e7d34c839ced8f22bddc39fb534978cc4

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