Merge changes from topic "mb/spm+rme-tb-mb-support" into integration

* changes:
fix(fvp): increase the maximum size of Event Log
fix(fvp): increase maximum MMAP and XLAT entries count
fix(arm)

Merge changes from topic "mb/spm+rme-tb-mb-support" into integration

* changes:
fix(fvp): increase the maximum size of Event Log
fix(fvp): increase maximum MMAP and XLAT entries count
fix(arm): add Event Log area behind Trustzone Controller
fix(tbbr): unrecognised 'tos-fw-key-cert' option

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feat(stm32mp2): generate stm32 file

To be able to boot, STM32MPU platforms require the BL2 binary (together
with its DT) to be preceded with an STM32 header. Add the required
files and macro to prop

feat(stm32mp2): generate stm32 file

To be able to boot, STM32MPU platforms require the BL2 binary (together
with its DT) to be preceded with an STM32 header. Add the required
files and macro to properly generate this header.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I675de2c5cb733fe9d9e9baf76a941741a06dfac8

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feat(stm32mp2): add console configuration

Use UART driver and fill helpers for crash console.
Add early console setup in bl2_el3_early_platform_setup().

Signed-off-by: Yann Gautier <yann.gautier@st

feat(stm32mp2): add console configuration

Use UART driver and fill helpers for crash console.
Add early console setup in bl2_el3_early_platform_setup().

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ifb39554214dec05dafe4e306f8754e1454cdab61

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feat(st): introduce new platform STM32MP2

This new STMicroelectronics SoC is based on a dual Cortex-A35.
For the moment, only BL2 is compiled with the common parts for ST
platforms.

Change-Id: I1bc

feat(st): introduce new platform STM32MP2

This new STMicroelectronics SoC is based on a dual Cortex-A35.
For the moment, only BL2 is compiled with the common parts for ST
platforms.

Change-Id: I1bc4e6835dba4230359ea9b26d736791e27258aa
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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refactor(st): move plat_image_load.c

This file is common for ST platforms, move it to plat/st/common/.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I7cefbc7f857d4ea63320042988c86d28

refactor(st): move plat_image_load.c

This file is common for ST platforms, move it to plat/st/common/.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I7cefbc7f857d4ea63320042988c86d28e8a3cc09

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refactor(st): rename PLAT_NB_FIXED_REGS

Rename PLAT_NB_FIXED_REGS to PLAT_NB_FIXED_REGUS.
This avoids confusion with regulators and registers.

Signed-off-by: Pascal Paillet <p.paillet@st.com>
Chang

refactor(st): rename PLAT_NB_FIXED_REGS

Rename PLAT_NB_FIXED_REGS to PLAT_NB_FIXED_REGUS.
This avoids confusion with regulators and registers.

Signed-off-by: Pascal Paillet <p.paillet@st.com>
Change-Id: Idb2de7204fe978ffcdd729e6cbe453e85fd089b5

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refactor(st): move some storage definitions to common part

Those storage macros are common to all STM32MPU chips, move them to
plat/st/common/include/stm32mp_io_storage.h

Signed-off-by: Yann Gautie

refactor(st): move some storage definitions to common part

Those storage macros are common to all STM32MPU chips, move them to
plat/st/common/include/stm32mp_io_storage.h

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Id20ec00ba65edf9ec7a3a89adfda307c954c3cb6

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refactor(st): move SDMMC definitions to driver

Those specific SDMMC definitions are only used in stm32_sdmmc2.c driver.
Move them there.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Chang

refactor(st): move SDMMC definitions to driver

Those specific SDMMC definitions are only used in stm32_sdmmc2.c driver.
Move them there.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Iac7e505e9421aa7630bee8ce6fc2277b98581995

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feat(st): allow AARCH64 compilation for common code

Use read_sctlr_el3() for aarch64 code instead of read_sctlr().

Change-Id: I17b5d1f8cb2918de6ab1d2d56c15cabca0ed43fd
Signed-off-by: Yann Gautier <

feat(st): allow AARCH64 compilation for common code

Use read_sctlr_el3() for aarch64 code instead of read_sctlr().

Change-Id: I17b5d1f8cb2918de6ab1d2d56c15cabca0ed43fd
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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refactor(st): rename QSPI macros

To have a more generic code, remove the Q from the *QSPI macros.

Change-Id: I2fa94b54054036c2175df3dfddcb76eec1119ad2
Signed-off-by: Yann Gautier <yann.gautier@st.c

refactor(st): rename QSPI macros

To have a more generic code, remove the Q from the *QSPI macros.

Change-Id: I2fa94b54054036c2175df3dfddcb76eec1119ad2
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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fix(fvp): increase the maximum size of Event Log

To make room for all image measurements using the
RME+SPM+TBB+MEASURED_BOOT test configuration, the Event Log's maximum
size has been significantly i

fix(fvp): increase the maximum size of Event Log

To make room for all image measurements using the
RME+SPM+TBB+MEASURED_BOOT test configuration, the Event Log's maximum
size has been significantly increased.

Change-Id: I0b9948dab893e14677bca0afa07167648a6c2729
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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fix(fvp): increase maximum MMAP and XLAT entries count

Maximum entries for MMAP and XLAT have been increased in order to
support the configuration SPM+RME, along with MEASURED_BOOT and
TRUSTED_BOARD

fix(fvp): increase maximum MMAP and XLAT entries count

Maximum entries for MMAP and XLAT have been increased in order to
support the configuration SPM+RME, along with MEASURED_BOOT and
TRUSTED_BOARD_BOOT.

Change-Id: Ic0a0aefecb49d7ccc71357c4bd94e7bd2e5f57c4
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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feat(qemu): add dummy plat_mboot_measure_key() BL1 function

Adds a dummy implementation of the plat_mboot_measure_key() function in
BL1 for QEMU platform.

Signed-off-by: Jens Wiklander <jens.wiklan

feat(qemu): add dummy plat_mboot_measure_key() BL1 function

Adds a dummy implementation of the plat_mboot_measure_key() function in
BL1 for QEMU platform.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Change-Id: I5923aad962a5e34d657cf49c177e68ed2ea93291

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Merge "fix(xilinx): don't reserve 1 more byte" into integration

Merge "feat(morello): add cpuidle support" into integration

Merge "fix(scmi): add parameter for plat_scmi_clock_rates_array" into integration

Merge "feat(imx8m): move the gpc reg & macro to a separate header file" into integration

Merge "feat(imx8m): add more dram pll setting" into integration

fix(xilinx): don't reserve 1 more byte

The commit f123b91fddfc ("fix(versal): fix BLXX memory
limits for user defined values") and commit a80da3899a5e
("fix(versal-net): fix BLXX memory limits for u

fix(xilinx): don't reserve 1 more byte

The commit f123b91fddfc ("fix(versal): fix BLXX memory
limits for user defined values") and commit a80da3899a5e
("fix(versal-net): fix BLXX memory limits for user defined
values") fixed issue regarding linker alignment section.
But removing -1 logic is not reflected in plat_fdt() memory
reservation code.
That's why remove +1 from prepare_dtb() not to generate a reserved
memory node with bigger size which ends up with reserving more
space than actually requested by a full featured bootloader or OS.

Change-Id: I0a646cee7d5a55157a6eb1b672c2edbe89e6a57f
Signed-off-by: Michal Simek <michal.simek@amd.com>

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Merge "fix(arm/fpga): enable CPU features required for ARMv9.2 cores" into integration

feat(morello): add cpuidle support

This patch adds necessary device-tree idle state definitions and enables
relevant platform makefile options.

Co-authored-by: Karl Meakin <karl.meakin@arm.com>
Sig

feat(morello): add cpuidle support

This patch adds necessary device-tree idle state definitions and enables
relevant platform makefile options.

Co-authored-by: Karl Meakin <karl.meakin@arm.com>
Signed-off-by: sahil <sahil@arm.com>
Change-Id: Iaf95867095f0514ec3994b9c9efd9756ed49ef43

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Merge "fix(ti): fix TISCI API changes during refactor" into integration

feat(imx8m): move the gpc reg & macro to a separate header file

move the gpc reg offset, bit define & macro to a separate header
file for code reuse.

This fixes suspend to mem on i.MX8M Plus too, s

feat(imx8m): move the gpc reg & macro to a separate header file

move the gpc reg offset, bit define & macro to a separate header
file for code reuse.

This fixes suspend to mem on i.MX8M Plus too, since the register
layout is different there.

Change-Id: Ibec60c3a68ffa8c378de5334577a7b0e463ca875
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Marek Vasut <marex@denx.de> # Upgrade to latest, update commit message

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feat(imx8m): add more dram pll setting

Add DRAM PLL frequency setting for 3732mts & 3733mts.

Change-Id: I74feab2185376bbb84826d7ee79b5e25cbc4d263
Signed-off-by: Marek Vasut <marex@denx.de>

fix(arm/fpga): enable CPU features required for ARMv9.2 cores

Similar to the FVP and QEMU, the Arm FPGA systems come with different
CPU cores, and gain new features over time.

Add a list of ARMv9.2

fix(arm/fpga): enable CPU features required for ARMv9.2 cores

Similar to the FVP and QEMU, the Arm FPGA systems come with different
CPU cores, and gain new features over time.

Add a list of ARMv9.2 features that require TF-A enablement to be usable
from non-secure world. Their existence will be detected at runtime, so
supporting all those features is not required for using the build.

This fixes the Linux kernel booting on a ARMv9.2 FPGA core.

Change-Id: Ie93c32b13ce4f9968081bf38296cd45edad0a928
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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