Merge "feat(mediatek): remove bl32 flag for mtk_bl" into integration

fix(sgi): reduce cper buffer carveout size

Reduce the size of the CPER buffer as it is overlapping with SP's heap
region.

Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: Iaea75a1f

fix(sgi): reduce cper buffer carveout size

Reduce the size of the CPER buffer as it is overlapping with SP's heap
region.

Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: Iaea75a1ffb50ecf0223594fe8bffcebc16da7eab

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fix(sgi): increase BL31 carveout size

With SPMC at el3 enabled on rdn2cfg2 configuration BL31 needs more
memory region to accommodate increased xlat table size.

Increase the size by 16K.

Signed-of

fix(sgi): increase BL31 carveout size

With SPMC at el3 enabled on rdn2cfg2 configuration BL31 needs more
memory region to accommodate increased xlat table size.

Increase the size by 16K.

Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: Ib235fe35d53a9b85a5ce0a29f2ec4cc3bd85ded9

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refactor(tc): deprecate Arm TC1 FVP platform

Arm has made the strategic decision to deprecate the TC1 platform.
Consequently, software development and the creation of fast models
for the TC1 platfor

refactor(tc): deprecate Arm TC1 FVP platform

Arm has made the strategic decision to deprecate the TC1 platform.
Consequently, software development and the creation of fast models
for the TC1 platform have been officially discontinued.
The TC1 platform, now considered obsolete, has been succeeded by
the TC2 platform. It's noteworthy that the TC2 platform is already
integrated and supported in both TF-A and CI repositories.

Change-Id: Ia196a5fc975b4dbf3c913333daf595199968d95d
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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feat(mediatek): remove bl32 flag for mtk_bl

Currently MediaTek platform code does not support the bl32 image.
Remove bl32 support from Makefile to prevent the build failure when
NEED_BL32 build flag

feat(mediatek): remove bl32 flag for mtk_bl

Currently MediaTek platform code does not support the bl32 image.
Remove bl32 support from Makefile to prevent the build failure when
NEED_BL32 build flag is enabled.

Change-Id: Id8d5663ea5c537390f8ff3ccb427a3a63266545e
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>

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refactor(qemu): change way how we enable cpu features

We have to handle wide selection of cpu cores in one TF-A binary:
- v8.0: a53, a57, a72
- v8.2: a55, a76, n1
- v8.4: v1
- v9.0: a710, n2

And th

refactor(qemu): change way how we enable cpu features

We have to handle wide selection of cpu cores in one TF-A binary:
- v8.0: a53, a57, a72
- v8.2: a55, a76, n1
- v8.4: v1
- v9.0: a710, n2

And then we have QEMU's hybrid: 'max' which has everything QEMU can
emulate.

TF-A for QEMU platforms was built for v8.5 architecture. But turned out
that 'max' has v8.7 flag now (HCX) which we need to have. And this
enabled set of mandatory features which made TF-A not-bootable on
v8.0/8.2 cpus.

So I decided to follow Arm FVP way and do build for v8.0 with set of
feature flags enabled. This way we have bare minimum to make v8.0 cpus
boot. And then all features from newer cores are enabled with runtime
check which makes them boot.

Tested with BSA/SBSA ACS and Debian Linux 6.5 kernel.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: Ib87bdab992536c65ce0747ce1520682eafc18d39
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

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refactor(fvp): remove RSS usage

Removed RSS usage from the Base AEM FVP platform, as it wasn't
functional on this platform. The Base AEM FVP platform lacks
support for RSS.
Instead, the TC2 platform

refactor(fvp): remove RSS usage

Removed RSS usage from the Base AEM FVP platform, as it wasn't
functional on this platform. The Base AEM FVP platform lacks
support for RSS.
Instead, the TC2 platform with RSS is available for actual RSS
interface implementation and testing.

Change-Id: I8f68157319399ab526f9e851b26dba903db5c2e7
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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fix(xilinx): update correct return types

Refactor the return types to ensure code correctness and compliance
for DT console.

Change-Id: I11dc3afbe168a78ddc03427df3f5f8d10fe40d40
Signed-off-by: Pras

fix(xilinx): update correct return types

Refactor the return types to ensure code correctness and compliance
for DT console.

Change-Id: I11dc3afbe168a78ddc03427df3f5f8d10fe40d40
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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fix(xilinx): add FIT image check in DT console

With this change, the 'is_valid_dtb()' function has been added,
which checks for the presence of the FDT header, FDT open, and the
'/configurations' pr

fix(xilinx): add FIT image check in DT console

With this change, the 'is_valid_dtb()' function has been added,
which checks for the presence of the FDT header, FDT open, and the
'/configurations' property in the DTB. This property is only available
in FIT images. If the property is present, a warning message is
printed, and the code skips reading console information from the
FIT image. Memory mapping is not necessary because it is called in
the early setup function to collect UART information from the DTB.

Change-Id: I91335a180e7ece2cc0ec9fac4026556c48dd8cc8
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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fix(xilinx): add FIT image check in prepare_dtb

Introduce two new functions: 'is_valid_image()' and 'is_fit_image()'
to enhance the functionality of the system. 'is_valid_image()' will
verify the pr

fix(xilinx): add FIT image check in prepare_dtb

Introduce two new functions: 'is_valid_image()' and 'is_fit_image()'
to enhance the functionality of the system. 'is_valid_image()' will
verify the presence of the FDT header and ensure that the FDT is
open. Meanwhile, 'is_fit_image()' will be responsible for detecting
FIT images. When TF-A is built with a DTB address during compilation
and later executed from DDR memory, TF-A will dynamically reserve a
memory location in the DTB during runtime.

This approach is effective when a raw DTB is present at the specified
address location. With this change, the "is_fit_image()" function
has been introduced to verify the existence of the "/configurations"
property within the DTB.

The presence of this property is exclusive to FIT images. In case
the property is found, a warning message is displayed, and memory
space reservation for its address space in DDR is not performed by
TF-A. However, if the property is not present, TF-A continues its
usual procedure of updating the raw DTB.

Additionally, dynamic mapping has been refactored and separated into
distinct functions: "add_mmap_dynamic_region ()" and
"remove_dynamic_mmap()". This separation enhances compatibility
and maintains better code organization.

Change-Id: I9cd3f09863b44483445e58c802dee34d58dfe2e9
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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fix(intel): read QSPI bank buffer data in bytes

Read QSPI bank buffer data in bytes to avoid
inter-bank read failures.

Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Change-Id: If768d7cdd36

fix(intel): read QSPI bank buffer data in bytes

Read QSPI bank buffer data in bytes to avoid
inter-bank read failures.

Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Change-Id: If768d7cdd362694df3f3c86c959afad01a523f21

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Merge "fix(arm): correct the SPMC_AT_EL3 condition" into integration

Merge "fix(intel): update boot scratch cold register to use cold 8" into integration

Merge changes from topic "sb/remove-cryptocell" into integration

* changes:
chore(npcm845x): remove CryptoCell-712/713 support
chore(auth)!: remove CryptoCell-712/713 support

Merge "docs(qemu): mention a55 in list of v8.2 cores" into integration

Merge "build(qemu): use xlat tables v2 directly" into integration

chore(npcm845x): remove CryptoCell-712/713 support

CryptoCell-712 and CryptoCell-713 drivers have been deprecated. Remove
their usage on Nuvoton npcm845x platform (maintainers confirmed that
this re

chore(npcm845x): remove CryptoCell-712/713 support

CryptoCell-712 and CryptoCell-713 drivers have been deprecated. Remove
their usage on Nuvoton npcm845x platform (maintainers confirmed that
this removal is fine with them).

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: I0e3f3431558aaea1e0f2740e7088cdc155d06af2

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build(qemu): use xlat tables v2 directly

Both qemu and qemu-sbsa use xlat tables v2 already (activated by including it
in common/common.mk) so there is no need to include compat headers.

Change-Id

build(qemu): use xlat tables v2 directly

Both qemu and qemu-sbsa use xlat tables v2 already (activated by including it
in common/common.mk) so there is no need to include compat headers.

Change-Id: I353a6f77f5916862e54b883a9adbba027ac81359
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

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docs(qemu): mention a55 in list of v8.2 cores

Change-Id: Ib3a1711be323023cf111373111f39038fa23fb6f
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

fix(arm): correct the SPMC_AT_EL3 condition

Addressed the SPMC_AT_EL3 condition by using '#if' instead of
'#if defined'. This change is warranted because the SPMC_AT_EL3
option is always defined.

C

fix(arm): correct the SPMC_AT_EL3 condition

Addressed the SPMC_AT_EL3 condition by using '#if' instead of
'#if defined'. This change is warranted because the SPMC_AT_EL3
option is always defined.

Change-Id: I76d9b8d502f452c58bc0040745d642cbe11dc8eb
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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chore(auth)!: remove CryptoCell-712/713 support

CryptoCell-712 and CryptoCell-713 drivers have been deprecated since
TF-A v2.9 and their removal was announced for TF-A v2.10 release.
See [1].

As th

chore(auth)!: remove CryptoCell-712/713 support

CryptoCell-712 and CryptoCell-713 drivers have been deprecated since
TF-A v2.9 and their removal was announced for TF-A v2.10 release.
See [1].

As the release is approaching, this patch deletes these drivers' code as
well as all references to them in the documentation and Arm platforms
code (Nuvoton platform is taken care in a subsequent patch). Associated
build options (ARM_CRYPTOCELL_INTEG and PLAT_CRYPTOCELL_BASE) have also
been removed and thus will have no effect if defined.

This is a breaking change for downstream platforms which use these
drivers.

[1] https://trustedfirmware-a.readthedocs.io/en/v2.9/about/release-information.html#removal-of-deprecated-drivers
Note that TF-A v3.0 release later got renumbered into v2.10.

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: Idabbc9115f6732ac1a0e52b273d3380677a39813

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Merge "build(qemu-sbsa): it is GICv3 platform" into integration

feat(sgi): increase sp memmap size

With FF-A enabled on SP at SEL0 enabled, SPMC at EL3 needs more entries
to map newly added regions(SP, Rx/Tx buffer and Manifest).

Increase the PLAT_SP_IMAGE_MMAP

feat(sgi): increase sp memmap size

With FF-A enabled on SP at SEL0 enabled, SPMC at EL3 needs more entries
to map newly added regions(SP, Rx/Tx buffer and Manifest).

Increase the PLAT_SP_IMAGE_MMAP_REGIONS to 14 and MAX_XLAT_TABLES to 9.

Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: I96fd291db8eb178f7aa73b5a9e38cfc67c66fa91

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feat(arm): save BL32 image base and size in entry point info

There is no platform function to retrieve the info in the generic code.
Populate the BL32 image base, size and max limit in arg2, arg3 an

feat(arm): save BL32 image base and size in entry point info

There is no platform function to retrieve the info in the generic code.
Populate the BL32 image base, size and max limit in arg2, arg3 and arg4.

Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: Id41cedd790ca1713787e5516fb84666d1ccb0b03

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build(qemu-sbsa): it is GICv3 platform

GICV2_G0_FOR_EL3 variable is only for GICv2 platforms.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: Ibf9376caabbc05ceef4f870d8

build(qemu-sbsa): it is GICv3 platform

GICV2_G0_FOR_EL3 variable is only for GICv2 platforms.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: Ibf9376caabbc05ceef4f870d816e6c60a344f895

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