Merge "fix(build): remove handling of mandatory options" into integration

Merge changes from topic "hm/mpam" into integration

* changes:
fix(build): convert tabs and ifdef comparisons
fix(build): disable ENABLE_FEAT_MPAM for Aarch32

Merge "refactor(fvp): do not use RSS platform token and attestation key APIs" into integration

fix(build): disable ENABLE_FEAT_MPAM for Aarch32

Disable FEAT_MPAM support for Aarch32 as it is not supported, following
[1]. ENABLE_FEAT_MPAM is set to 2 by default for Aarch64 in
arch_features.mk,

fix(build): disable ENABLE_FEAT_MPAM for Aarch32

Disable FEAT_MPAM support for Aarch32 as it is not supported, following
[1]. ENABLE_FEAT_MPAM is set to 2 by default for Aarch64 in
arch_features.mk, eliminating the need for duplication in the platform
makefile.

[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/23710

Change-Id: I1c8b6844254e00e6372900f1c87f995f292ae65c
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

show more ...

fix(corstone-1000): removing the signature area

The TF-M on the secure enclave side takes care of boot bank selection for our platform. The TF-A doesn't require to manage the boot bank, so,
removing

fix(corstone-1000): removing the signature area

The TF-M on the secure enclave side takes care of boot bank selection for our platform. The TF-A doesn't require to manage the boot bank, so,
removing the boot bank selection. TF-A doesn't expect the signature area so removed it from FIP partition

Change-Id: I298dd51fa068534c299c66b0e4c353819ea12a26
Signed-off-by: Mohamed Omar Asaker <mohamed.omarasaker@arm.com>
Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>

show more ...

Merge changes from topic "hm/post-image" into integration

* changes:
refactor(fvp): move image handling into generic procedure
refactor(bl2): make post image handling platform-specific

feat(zynqmp): enable assertion

Retain assertions in builds for TF-A run from DDR with
ENABLE_ASSERTIONS=1. It helps to catch programming errors
(e.g. bad argument provided by platform porting functi

feat(zynqmp): enable assertion

Retain assertions in builds for TF-A run from DDR with
ENABLE_ASSERTIONS=1. It helps to catch programming errors
(e.g. bad argument provided by platform porting function)
code size change is 4k.
For debug builds, assertions are enabled by default.
The same change is done by Tegra: plat/nvidia/tegra/platform.mk.

Change-Id: I1790862616faddf68b4d533750722dad27cae269
Signed-off-by: Amit Nagal <amit.nagal@amd.com>

show more ...

feat(versal-net): enable assertion

Retain assertions in release builds by building TF-A with
ENABLE_ASSERTIONS=1. It helps to catch programming errors
(e.g. bad argument provided by platform porting

feat(versal-net): enable assertion

Retain assertions in release builds by building TF-A with
ENABLE_ASSERTIONS=1. It helps to catch programming errors
(e.g. bad argument provided by platform porting function)
in release builds as well.
code size change is 4k.
For debug builds, assertions are enabled by default.
The same change is done by Tegra: plat/nvidia/tegra/platform.mk

Change-Id: I0db4b82d42d115866a3ed43933edbfc46ac7406a
Signed-off-by: Amit Nagal <amit.nagal@amd.com>

show more ...

feat(versal): enable assertion

Retain assertions in release builds by building TF-A with
ENABLE_ASSERTIONS=1. It helps to catch programming errors
(e.g. bad argument provided by platform porting fun

feat(versal): enable assertion

Retain assertions in release builds by building TF-A with
ENABLE_ASSERTIONS=1. It helps to catch programming errors
(e.g. bad argument provided by platform porting function)
in release builds as well.
code size change is 4k.
For debug builds, assertions are enabled by default.
The same change is done by Tegra: plat/nvidia/tegra/platform.mk.

Change-Id: Ie801fa9a326596ebef71be870b95a3cf9077ad20
Signed-off-by: Amit Nagal <amit.nagal@amd.com>

show more ...

Merge "fix(versal): type cast addresses to fix integer overflow" into integration

fix(build): remove handling of mandatory options

With commit@f5211420b(refactor(cpufeat): refactor arch feature build
options all mandatory options are enabled with
'make_helpers/arch_features.mk' s

fix(build): remove handling of mandatory options

With commit@f5211420b(refactor(cpufeat): refactor arch feature build
options all mandatory options are enabled with
'make_helpers/arch_features.mk' so avoid enabling of mandatory features
in platform makefile.

Use correct Arch Major/Minor to get all the mandatory features enabled
by default.

Change-Id: Ia214aa75dc9caea949f697ecafb1ef1812c6d899
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

show more ...

Merge changes from topic "gr/build_refactor" into integration

* changes:
build(refactor): avoid ifdef comparison
refactor(build): avoid using values for comparison
refactor(build): reorder arc

Merge changes from topic "gr/build_refactor" into integration

* changes:
build(refactor): avoid ifdef comparison
refactor(build): avoid using values for comparison
refactor(build): reorder arch features handling
build(n1sdp): add ARM_ARCH_MAJOR.ARM_ARCH_MINOR
refactor(build): reorder platform Makefile evaluation

show more ...

refactor(build): avoid using values for comparison

With changes to refactor to use first platform makefiles
then parse arch_features.mk file 'ENABLE_RME' will be initialised
only when we define duri

refactor(build): avoid using values for comparison

With changes to refactor to use first platform makefiles
then parse arch_features.mk file 'ENABLE_RME' will be initialised
only when we define during build or at arch_features.mk thus
making comparison of 'ENABLE_RME' to '0' incorrect.

So keep BRBE disabled when RME is enabled at main makefile level.

Change-Id: I7e3d99eb444678d63585bd5971ada627cfc4fcc9
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

show more ...

build(n1sdp): add ARM_ARCH_MAJOR.ARM_ARCH_MINOR

n1sdp based out of Arm Neoverse N1 Core uses Arm®v8.2‑A extensions
so set ARM_ARCH_MAJOR.ARM_ARCH_MINOR for n1sdp platform to 8.2

Change-Id: Ib70c6be

build(n1sdp): add ARM_ARCH_MAJOR.ARM_ARCH_MINOR

n1sdp based out of Arm Neoverse N1 Core uses Arm®v8.2‑A extensions
so set ARM_ARCH_MAJOR.ARM_ARCH_MINOR for n1sdp platform to 8.2

Change-Id: Ib70c6be5e12817961430870d50fb1b0efca32df2
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

show more ...

Merge changes from topic "mb/psa-crypto-ecdsa" into integration

* changes:
docs: mark PSA_CRYPTO as an experimental feature
feat(fvp): increase BL1 RW area for PSA_CRYPTO implementation
feat(m

Merge changes from topic "mb/psa-crypto-ecdsa" into integration

* changes:
docs: mark PSA_CRYPTO as an experimental feature
feat(fvp): increase BL1 RW area for PSA_CRYPTO implementation
feat(mbedtls-psa): mbedTLS PSA Crypto with ECDSA

show more ...

fix(versal): type cast addresses to fix integer overflow

Typecast the base and size arguments for build time as unsigned
integers and the limit derived from these two as an unsigned long
to prevent

fix(versal): type cast addresses to fix integer overflow

Typecast the base and size arguments for build time as unsigned
integers and the limit derived from these two as an unsigned long
to prevent size integer overflow issues during the build.

Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: Iefc148e0091e8c8a4ca505691036c79528a558a4

show more ...

refactor(fvp): move image handling into generic procedure

Post image handling of the HW_CONFIG is out-of-scope for
`plat_get_next_bl_params`. Move parts of the code responsible for post
processing o

refactor(fvp): move image handling into generic procedure

Post image handling of the HW_CONFIG is out-of-scope for
`plat_get_next_bl_params`. Move parts of the code responsible for post
processing of loaded images into `bl2_plat_handle_post_image_load` for code
reusability and maintainability.

Change-Id: I476b3d306ebcd4529f5e542ba1063e144920bb5f
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

show more ...

refactor(bl2): make post image handling platform-specific

In certain instances a platform may need to make modifications to an
image after it has been loaded by BL2. The existing common
implementati

refactor(bl2): make post image handling platform-specific

In certain instances a platform may need to make modifications to an
image after it has been loaded by BL2. The existing common
implementation is a thin wrapper for a more generic arm post image
handler. To enable platforms to make changes to images when
they're loaded, move this into platform code.

Change-Id: I44025391056adb2d8a8eb4ea5984257b02027181
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

show more ...

fix(ast2700): add device mapping for coherent memory

The coherent memory should be mapped as Device nGnRnE.
This fix adds the missing MMU attributes for coherent memory
if enabled.

Signed-off-by: C

fix(ast2700): add device mapping for coherent memory

The coherent memory should be mapped as Device nGnRnE.
This fix adds the missing MMU attributes for coherent memory
if enabled.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Change-Id: I90b8de167c48f03392c9740f88f4b1e7b073a82d

show more ...

feat(ti): query firmware for suspend capability

Instead of hardcoding this at build time we can ask the firmware if
suspend is supported and if not disable accordingly. Then remove compile-
time ifd

feat(ti): query firmware for suspend capability

Instead of hardcoding this at build time we can ask the firmware if
suspend is supported and if not disable accordingly. Then remove compile-
time ifdefs.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: Ib966c04c0bdb79a82e8d890cec5e65d883acd6e3

show more ...

feat(ti): add TI-SCI query firmware capabilities command support

This TISCI API is used to retrieve the firmware capabilities of the
currently running system-firmware.

Signed-off-by: Andrew Davis <

feat(ti): add TI-SCI query firmware capabilities command support

This TISCI API is used to retrieve the firmware capabilities of the
currently running system-firmware.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I55402dcf876e997eb21bb1f31c725e167c507c47

show more ...

feat(ti): remove extra core counts in cluster 2 and 3

No K3 SoC supported by this TARGET_BOARD has any cluster
2 or 3 cores. Remove these to save some memory.

Signed-off-by: Andrew Davis <afd@ti.co

feat(ti): remove extra core counts in cluster 2 and 3

No K3 SoC supported by this TARGET_BOARD has any cluster
2 or 3 cores. Remove these to save some memory.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I27868a2f3aac25fa0fdec56847e273d88f0d9a87

show more ...

Merge changes from topic "gpt_updates" into integration

* changes:
refactor(arm): use gpt_partition_init
feat(partition): add interface to init gpt
refactor(partition): convert warn to verbose

Merge changes from topic "gpt_updates" into integration

* changes:
refactor(arm): use gpt_partition_init
feat(partition): add interface to init gpt
refactor(partition): convert warn to verbose
feat(partition): add support to use backup GPT header
refactor(partition): get GPT header location from MBR
feat(arm): add IO policy to use backup gpt header
feat(tbbr): add image id for backup GPT

show more ...

Merge "feat(cpus): add support for Travis CPU" into integration

Merge "fix(ti): align static device region addresses to reduce MMU table count" into integration