feat(versal-net): add bufferless IPI Support

There exist inter-processor interrupts on Versal-Net that do not have
corresponding message buffers. These bufferless IPI's on Versal NET
SOC are added t

feat(versal-net): add bufferless IPI Support

There exist inter-processor interrupts on Versal-Net that do not have
corresponding message buffers. These bufferless IPI's on Versal NET
SOC are added to static IPI Tables.

In hardware description there exists two IPI's called 'IPI6' without
buffers that have respective system interrupt values 95 and 101. For
these append the string '_95' or '_101' to denote the difference for
each.

Change-Id: I22bf1a68cb0ed68913eb868f1c197856fc7d82d5
Signed-off-by: Ben Levinsky <ben.levinsky@amd.com>

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feat(tc): provide a mock mbedtls-random generation function

Simulated the utilization of an external RNG through the
MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG configuration option in mbedTLS.
Consequently, an

feat(tc): provide a mock mbedtls-random generation function

Simulated the utilization of an external RNG through the
MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG configuration option in mbedTLS.
Consequently, an implementation of mbedtls_psa_external_get_random()
is provided. Given the absence of actual external RNG support,
we provide a mock implementation by utilizing the system counter to
fill the the buffer to provide a random number, specifically tailored
for the use exclusively within the TF-M testsuite.
While this method is not ideal for generating random numbers,
alternatives like the 'rand' library function are not feasible due to
lack of support in TF-A. Additionally, the architectural 'rand'
instruction is not viable, as it is only supported for platforms with
Armv8.5-a+ architecture as an optional feature.
mbedtls_psa_external_get_random() function comes into play during the
exportation of the public portion of the delegated attestation key.

This helps in using mbedTLS-3.4.1 for running the delegated attestation
tests on TC platform.

Change-Id: Ifcf4e3231aad93595e00c353a4b0c606c0ef9fc2
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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build(versal-net): reorganize platform source files

Reorganize the platform source files necessary across various
Bootloader (BL) configurations within the platform makefile.
This reordering aims to

build(versal-net): reorganize platform source files

Reorganize the platform source files necessary across various
Bootloader (BL) configurations within the platform makefile.
This reordering aims to prevent redundant inclusions of these files
across multiple makefiles used for distinct features.

Change-Id: I9c5525dd8522cb8c8e3ad6add70189dcb7cfcc29
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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feat(imx8m): add 3600 MTps DDR PLL rate

Add 3600 MTps DRAM and its 900 MHz PLL setting M=300 P=8 S=0 , so
24 MHz * 300 / 8 / 2^0 = 900 MHz ~ 3600 MTps (x4) .

Signed-off-by: Marek Vasut <marex@denx.

feat(imx8m): add 3600 MTps DDR PLL rate

Add 3600 MTps DRAM and its 900 MHz PLL setting M=300 P=8 S=0 , so
24 MHz * 300 / 8 / 2^0 = 900 MHz ~ 3600 MTps (x4) .

Signed-off-by: Marek Vasut <marex@denx.de>
Change-Id: If2743827294efc0f981718f04b772cc462846195

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fix(imx8m): align 3200 MTps rate with U-Boot

The 3200 MTps DRAM and its 800 MHz PLL setting in U-Boot is set to
M=300 P=9 S=0 , so 24 MHz * 300 / 9 / 2^0 = 800 MHz ~ 3200 MTps (x4) .
Make sure the P

fix(imx8m): align 3200 MTps rate with U-Boot

The 3200 MTps DRAM and its 800 MHz PLL setting in U-Boot is set to
M=300 P=9 S=0 , so 24 MHz * 300 / 9 / 2^0 = 800 MHz ~ 3200 MTps (x4) .
Make sure the PLL settings are aligned across software components.

Signed-off-by: Marek Vasut <marex@denx.de>
Change-Id: I163f81696be213acf6ecebe89ff2c76d41484cc5

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fix(imx8m): handle 3734 in addition to 3733 and 3732 MTps rates

The new MX8M DDR tool 3.31 now generates a programming file which uses
data rate 3734 instead of 3733 or 3732 . Handle another roundin

fix(imx8m): handle 3734 in addition to 3733 and 3732 MTps rates

The new MX8M DDR tool 3.31 now generates a programming file which uses
data rate 3734 instead of 3733 or 3732 . Handle another rounding option .

Signed-off-by: Marek Vasut <marex@denx.de>
Change-Id: I97a69650c12d78dfff9dcdb23e27fd6590f57fc0

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Merge "feat(ff-a): update FF-A version to v1.2" into integration

feat(mt8188): add secure iommu support

The secure IOMMU has two secure banks: VDO and VPP. Add SiP call to
report the secure bank status in debug build.
About more background, please see:
https://gi

feat(mt8188): add secure iommu support

The secure IOMMU has two secure banks: VDO and VPP. Add SiP call to
report the secure bank status in debug build.
About more background, please see:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/include/dt-bindings/memory/mediatek,mt8188-memory-port.h?id=d5cda142d649c690fb0fcf1e29f3df63fbafc442

Change-Id: I7b3319e84391fc6d7f456659f8b8c5d9d1c6ab9d
Signed-off-by: Anan Sun <anan.sun@mediatek.corp-partner.google.com>
Signed-off-by: Kiwi Liu <kiwi.liu@mediatek.corp-partner.google.com>
Signed-off-by: Yong Wu <yong.wu@mediatek.com>

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feat(ff-a): update FF-A version to v1.2

Bump the required FF-A version in framework and manifests to v1.2 as
upstream feature development goes.

Signed-off-by: Kathleen Capella <kathleen.capella@arm

feat(ff-a): update FF-A version to v1.2

Bump the required FF-A version in framework and manifests to v1.2 as
upstream feature development goes.

Signed-off-by: Kathleen Capella <kathleen.capella@arm.com>
Change-Id: I09d936d4aad89965cfd13f58741d647223b63a34

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Merge changes from topic "ns/spmc_at_el3" into integration

* changes:
feat(rdn2): add dts for secure partition
feat(el3-spmc): synchronize access to the s-el0 sp context
feat(el3-spmc): add su

Merge changes from topic "ns/spmc_at_el3" into integration

* changes:
feat(rdn2): add dts for secure partition
feat(el3-spmc): synchronize access to the s-el0 sp context
feat(el3-spmc): add support to map S-EL0 SP device regions
feat(el3-spmc): add support to map S-EL0 SP memory regions
feat(el3-spmc): add support for FFA_MEM_PERM_GET and SET ABIs
feat(el3-spmc): add support to setup S-EL0 context

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feat(rdn2): add dts for secure partition

This patch adds dts for Standalone MM used as S-EL0 SP on RD-N2
platform.

Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
Signed-off-by: Nish

feat(rdn2): add dts for secure partition

This patch adds dts for Standalone MM used as S-EL0 SP on RD-N2
platform.

Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: I9f1a6825d43f8be1c4bdeb98d9d7267b595e2b76

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Merge "feat(neoverse): enable NEOVERSE_Nx_EXTERNAL_LLC flag" into integration

feat(neoverse): enable NEOVERSE_Nx_EXTERNAL_LLC flag

Neoverse reference design platforms include a system level cache in the
interconnect and that is the last level cache. So enable the build flag
'

feat(neoverse): enable NEOVERSE_Nx_EXTERNAL_LLC flag

Neoverse reference design platforms include a system level cache in the
interconnect and that is the last level cache. So enable the build flag
'NEOVERSE_Nx_EXTERNAL_LLC' for all the Neoverse reference design
platforms.

Change-Id: I813b3ef7ea7dc4e335b44a88e019d8c56f05f4ac
Signed-off-by: Nuno Lopes <nuno.lopes@arm.com>

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Merge "fix(rk3328): apply ERRATA_A53_1530924 erratum" into integration

Merge changes from topic "xlnx_fitimage_check" into integration

* changes:
fix(xilinx): update correct return types
fix(xilinx): add FIT image check in DT console
fix(xilinx): add FIT image ch

Merge changes from topic "xlnx_fitimage_check" into integration

* changes:
fix(xilinx): update correct return types
fix(xilinx): add FIT image check in DT console
fix(xilinx): add FIT image check in prepare_dtb

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Merge "fix(intel): read QSPI bank buffer data in bytes" into integration

Merge "fix(intel): temporarily workaround for Zephyr SMP" into integration

Merge "feat(intel): restructure watchdog" into integration

fix(rk3328): apply ERRATA_A53_1530924 erratum

Apply erratum ERRATA_A53_1530924.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Ib4130fd9d4cd16b12322f44e91196607fcb6bf6b

Merge "fix(intel): update individual return result for hps and fpga bridges" into integration

Merge "feat(intel): increase bl2 size limit" into integration

Merge "fix(intel): update stream id to non-secure for SDM" into integration

Merge "fix(intel): revert sys counter to 400MHz" into integration

Merge changes from topic "mb/deprecate-rss-for-fvp" into integration

* changes:
refactor(fvp): remove RSS usage
refactor(rss)!: remove PLAT_RSS_NOT_SUPPORTED build option

Merge changes from topic "ns/spmc_at_el3" into integration

* changes:
fix(sgi): reduce cper buffer carveout size
fix(sgi): increase BL31 carveout size