feat(stm32mp2): add plat_my_core_pos

This function is required, at least for bakery locks.

Change-Id: I28906c50e0a0ebff5d387a424247513ec1a599fc
Signed-off-by: Yann Gautier <yann.gautier@st.com>

fix(stm32mp2): correct early/crash console init

The former code, using x2 register, was removing the LPEN bit from UART
config register. So the UART clock is stopped as soon as the CA35 is in
CSleep

fix(stm32mp2): correct early/crash console init

The former code, using x2 register, was removing the LPEN bit from UART
config register. So the UART clock is stopped as soon as the CA35 is in
CSleep. It was then displaying crap in Linux console.
The ands check instruction is replaced with a clearer tst instruction
directly with the bit to be tested.

Change-Id: I8a2b3ab195981dee2962e0c2f5d501d5933c17f4
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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Merge changes from topic "drop-dt-from-edk2/cpu" into integration

* changes:
docs(qemu-sbsa): describe what we get from QEMU
feat(qemu-sbsa): handle CPU information

docs(qemu-sbsa): describe what we get from QEMU

QEMU provides us with minimal information about hardware platform using
minimalistic DeviceTree. This is not a Linux DeviceTree. It is not even
a firm

docs(qemu-sbsa): describe what we get from QEMU

QEMU provides us with minimal information about hardware platform using
minimalistic DeviceTree. This is not a Linux DeviceTree. It is not even
a firmware DeviceTree.

Change-Id: I7b6cc5f53a4f78a9ed69bc7fc2fa1a69ea65428d
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

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feat(qemu-sbsa): handle CPU information

We want to remove use of DeviceTree from EDK2. So we move
functions to TF-A:

- counting cpu cores
- checking NUMA node id
- checking MPIDR

And then it gets

feat(qemu-sbsa): handle CPU information

We want to remove use of DeviceTree from EDK2. So we move
functions to TF-A:

- counting cpu cores
- checking NUMA node id
- checking MPIDR

And then it gets passed to EDK2 via SMC calls.

Change-Id: I1c7fc234ba90ba32433b6e4aa2cf127f26da00fd
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

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Merge "feat(imx8m): make bl33 start configurable via PRELOADED_BL33_BASE" into integration

Merge "feat(intel): support wipe DDR after calibration" into integration

Merge "fix(intel): update from INFO to VERBOSE when print debug message" into integration

feat(versal): extend platform address space sizes

The AMD-Xilinx Versal platform, currently only supports the OCM and
Low DDR address ranges in both physical and virtual address range.
To locate and

feat(versal): extend platform address space sizes

The AMD-Xilinx Versal platform, currently only supports the OCM and
Low DDR address ranges in both physical and virtual address range.
To locate and execute TF-A from High DDR and HBM address range,
expanding the address scope is necessary.

Depending on the BL31_BASE address both the platform physical and
virtual space sizes are selected.

Change-Id: I49112bff9eda44d924c5f49ea99aed9a8d5e5774
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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Merge changes Id85b2541,I4d253e2f into integration

* changes:
fix(intel): update system counter back to 400MHz
fix(intel): revert back to use L4 clock

Merge "fix(intel): update fcs crypto init code to check for mode" into integration

Merge changes from topic "cpu_trp_rotpk_fixes" into integration

* changes:
fix(rotpk): move rotpk definitions out of arm_def.h
feat(cpu): add support for Poseidon V CPU
fix(cpu): correct varia

Merge changes from topic "cpu_trp_rotpk_fixes" into integration

* changes:
fix(rotpk): move rotpk definitions out of arm_def.h
feat(cpu): add support for Poseidon V CPU
fix(cpu): correct variant name for default Poseidon CPU
fix(rmmd): avoid TRP when external RMM is defined

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feat(imx8m): make bl33 start configurable via PRELOADED_BL33_BASE

The TF-A does have a official PRELOADED_BL33_BASE define which is used
to tell the TF-A where to jump and that no bl33 loading is re

feat(imx8m): make bl33 start configurable via PRELOADED_BL33_BASE

The TF-A does have a official PRELOADED_BL33_BASE define which is used
to tell the TF-A where to jump and that no bl33 loading is requied. Use
this to make the platform specific PLAT_NS_IMAGE_OFFSET configurable.

This becomes necessary if one would like to place the bl33 code to other
places.

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Change-Id: I9d462c0e9df8e6d2ad78ee770bfa59e680739a51

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fix(xilinx): add console_flush() before shutdown

Add console_flush() call before shutting down in order to
ensure that console output is flushed.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@a

fix(xilinx): add console_flush() before shutdown

Add console_flush() call before shutting down in order to
ensure that console output is flushed.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I5397105d2d7bf317f199b6326593bdb1c3cc75e2

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fix(xilinx): fix sending sgi to linux

Currently in Versal NET TF-A writing 32 bits in icc_asgi1r_el1 register
to raise SGI to Linux but this register is of 64 bits. Also its writing
only CPU number

fix(xilinx): fix sending sgi to linux

Currently in Versal NET TF-A writing 32 bits in icc_asgi1r_el1 register
to raise SGI to Linux but this register is of 64 bits. Also its writing
only CPU number and SGI number to this register but along with that it
needs to write cluster number and other information. Which is not happening
currently. So use generic function plat_ic_raise_ns_sgi() to raise SGI to
Linux.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I6f5146c8315a321b705ed2ef79e2dc927b805ffb

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feat(xilinx): add new state to identify cpu power down

Currently there is only 1 state for CPU idle which is used while CPU
power down from Linux CPU idle feature. But CPU power down when firmware
s

feat(xilinx): add new state to identify cpu power down

Currently there is only 1 state for CPU idle which is used while CPU
power down from Linux CPU idle feature. But CPU power down when firmware
send CPU power down request needs new state in self suspend to
distinguish in firmware for CPU power down from power down request or CPU
power down from Linux CPU idle. So add new state PM_STATE_CPU_OFF to
indicate CPU power down from power down request from firmware.

PM_STATE_CPU_OFF state is supported from self-suspend version 3. So
added feature check which sends new state in case of new firmware and
old state i.e. PM_STATE_CPU_IDLE in case of old firmware.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I4118e1b813e5f76fca7b7e9ca1cc598715203fb0

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feat(xilinx): request cpu power down from reset

Send subsystem restart notification to firmware when TF-A receives
system reset PSCI call. On receiving subsystem restart call, firmware
will send CPU

feat(xilinx): request cpu power down from reset

Send subsystem restart notification to firmware when TF-A receives
system reset PSCI call. On receiving subsystem restart call, firmware
will send CPU idle callback to TF-A for powering down all cores. Wait
for CPU idle callback from firmware and raise power down request to
all cores after it receives CPU idle callback to power down core.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I50f417ae228017f38b648740dc90b2e8f1872620

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feat(xilinx): power down all cores on receiving cpu pwrdwn req

On receiving CPU power down request from firmware, TF-A raises SGI
interrupt to all active cores for entering in power down state. So a

feat(xilinx): power down all cores on receiving cpu pwrdwn req

On receiving CPU power down request from firmware, TF-A raises SGI
interrupt to all active cores for entering in power down state. So add support
for power down core on receiving CPU power down request. PWRDWN_WAIT_TIMEOUT
is the timeout value in milliseconds for the other cores to transition to
power down state.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I29760a2098852c546fa5a1324262a62c3d75b391

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feat(xilinx): add handler for power down req sgi irq

On receiving CPU power down callback, TF-A raises SGI interrupt to all active
cores to power down each active cores. Add handler for this SGI IRQ

feat(xilinx): add handler for power down req sgi irq

On receiving CPU power down callback, TF-A raises SGI interrupt to all active
cores to power down each active cores. Add handler for this SGI IRQ.

By default TF-A uses SGI 6 for CPU power down request. This can be
configurable through CPU_PWRDWN_SGI build flag.

e.g., If user wants to use SGI 7 instead of SGI 6 then provide build
flag CPU_PWRDWN_SGI=7

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: Id0df32187d1de3f0af4486eb4d4930cb3ab01dbd

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feat(xilinx): add wrapper to handle cpu power down req

Firmware sends CPU power down request to TF-A through NOTIFY_CB
callback. It indicates CPU needs to power down.

Add wrapper to handle CPU powe

feat(xilinx): add wrapper to handle cpu power down req

Firmware sends CPU power down request to TF-A through NOTIFY_CB
callback. It indicates CPU needs to power down.

Add wrapper to handle CPU power down request from firmware
through IPI callback.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: Ic4aff874dd29da057c5ffde1899c7f0e5cdf6733

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fix(versal-net): use arm common GIC handlers

Currently SGI interrupts are not received in secondary cores because
of issue in GIC configuration. In current Versal NET specific GIC
functions, redist

fix(versal-net): use arm common GIC handlers

Currently SGI interrupts are not received in secondary cores because
of issue in GIC configuration. In current Versal NET specific GIC
functions, redistributor configuration is not happening properly.
Because of that SGI interrupt from one processor to another processor
is not transferring. So, use common GIC handlers which will iterate
over all GIC redistributor frames and discovers per cpu redistributor
frame. Also, it initializes corresponding interface in GICv3.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I1433260b8520d6a315fdf5df86bd0688f92d211a

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fix(xilinx): rename macros to align with ARM

Use generic macro name as per common ARM GIC macro name for Versal
and Versal NET.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id:

fix(xilinx): rename macros to align with ARM

Use generic macro name as per common ARM GIC macro name for Versal
and Versal NET.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I2987ff2f612993fc80979f0179c04d316259ed1d

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feat(qemu): support TRP for RME

When an external RMM is not provided during make invocation, include the
Test Realm Payload (TRP) to the FIP.

Change-Id: I15d396cf268a08d79da63075aadb4172238eb225
Si

feat(qemu): support TRP for RME

When an external RMM is not provided during make invocation, include the
Test Realm Payload (TRP) to the FIP.

Change-Id: I15d396cf268a08d79da63075aadb4172238eb225
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>

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feat(qemu): load and run RMM image

When RME is enabled, jump to the RMM image before BL33. When using
semihosting rather than FIP, the image called "rmm.bin" is loaded from
the runtime directory.

C

feat(qemu): load and run RMM image

When RME is enabled, jump to the RMM image before BL33. When using
semihosting rather than FIP, the image called "rmm.bin" is loaded from
the runtime directory.

Change-Id: I15863410b1e505aa502276b339b22a2ddcb0b745
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>

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feat(qemu): setup Granule Protection Table

When RME is enabled, call the GPT library to setup the granule
protection tables and partition the physical address space.

Change-Id: Ib466c4579ff55fcff93

feat(qemu): setup Granule Protection Table

When RME is enabled, call the GPT library to setup the granule
protection tables and partition the physical address space.

Change-Id: Ib466c4579ff55fcff9307550e6d26d432674779a
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>

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