fix(tc): do not enable MPMM and Aux AMU counters always

There are requirements in which the MPMM and Auxiliary AMU counters have
to be disabled. Hence removing the "override" here which helps in
dis

fix(tc): do not enable MPMM and Aux AMU counters always

There are requirements in which the MPMM and Auxiliary AMU counters have
to be disabled. Hence removing the "override" here which helps in
disabling them during the build.

Change-Id: I2c0a808d5d9968082a508a9206e34f7a57f2e33a
Signed-off-by: Davidson K <davidson.kumaresan@arm.com>

show more ...

fix(spm): reduce verbosity on passing tf-a-tests

Reduce info messages verbosity for RME test cases:

INFO: Sip Call - Protect memory
INFO: Sip Call - Unprotect memory
INFO: Sip Call - Prote

fix(spm): reduce verbosity on passing tf-a-tests

Reduce info messages verbosity for RME test cases:

INFO: Sip Call - Protect memory
INFO: Sip Call - Unprotect memory
INFO: Sip Call - Protect memory
INFO: Sip Call - Unprotect memory

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I0bdb545bc6576110dd740ecda8130618f51ed710

show more ...

refactor(sgi): replace references to "SGI"/"sgi" for neoverse_rd

Currently, there are several reference to "SGI" or "sgi" in comments or
as macro prefix within the neoverse_rd directory. As part of

refactor(sgi): replace references to "SGI"/"sgi" for neoverse_rd

Currently, there are several reference to "SGI" or "sgi" in comments or
as macro prefix within the neoverse_rd directory. As part of the
migration to neoverse_rd, rename all occurences of "SGI/sgi" to
"Neoverse-RD" or the "NRD" prefix accordingly. All references in
comments are rephrased as "Neoverse RD platforms". References in code
are renamed as "NRD"/"nrd" accordingly.

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: Iec195427ff2bee565cb4a325a1a22892be95ae16

show more ...

refactor(sgi): rename "CSS_SGI"" macro prefixes to "NRD"

As of now, several internal macros utilize "CSS_SGI" as their prefix.
Given the change to neoverse_rd, and the subsequent migration out of th

refactor(sgi): rename "CSS_SGI"" macro prefixes to "NRD"

As of now, several internal macros utilize "CSS_SGI" as their prefix.
Given the change to neoverse_rd, and the subsequent migration out of the
css directory, the prefix "CSS_SGI" is no longer appropriate.
Therefore, update the macro prefixes to "NRD" for consistency and
clarity.

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: I3d1a9dba3e83f6e107379fc5bcf8256cc93d8c3d

show more ...

refactor(sgi): move apis and types to "nrd" prefix

Currently, functions and types internal to "neoverse_rd" platforms are
named with "sgi" as the prefix. Since common code and platforms are no
longe

refactor(sgi): move apis and types to "nrd" prefix

Currently, functions and types internal to "neoverse_rd" platforms are
named with "sgi" as the prefix. Since common code and platforms are no
longer under the "sgi" umbrella, move the prefix to "nrd". This change
would amend the prefixes for functions, types and objects.

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: I706a82bddf55c3be7cf9cef9aaa5df6d420098ca

show more ...

refactor(sgi): replace build-option prefix to "NRD"

As of now, CSS_SGI_PLATFORM_VARIANT and CSS_SGI_CHIP_COUNT are the
external build option that "sgi" platforms support. As "sgi" has been
renamed t

refactor(sgi): replace build-option prefix to "NRD"

As of now, CSS_SGI_PLATFORM_VARIANT and CSS_SGI_CHIP_COUNT are the
external build option that "sgi" platforms support. As "sgi" has been
renamed to "neoverse_rd" and the source files have been migrated out of
the css directory, replace the prefix "CSS_SGI" with "NRD".

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: I27989ff42404d823dd2a8cd22ff485497ccb62d4

show more ...

refactor(sgi): move neoverse_rd out of css

Currently, neoverse_rd is hosted under the "css" directory. However,
"css" directory is more relevant for hosting css definitions and
corresponding sources

refactor(sgi): move neoverse_rd out of css

Currently, neoverse_rd is hosted under the "css" directory. However,
"css" directory is more relevant for hosting css definitions and
corresponding sources. Since neoverse_rd hosts source and header for css
and soc, move neoverse_rd from css to board folder. Consolidate common
sources and headers under neoverse_rd/common. Additionally, group RD-V1,
RD-V1-MC, RD-N2, RD-N1-Edgex2 and SGI-575 within neoverse_rd/platform.
With the changes in this commit, the tree view would look as follows:

plat/arm/board/neoverse_rd/
├── common
│   ├── arch
│   ├── include
│   └── ras
└── platform
├── rdn1edge
├── rdn2
├── rdv1
├── rdv1mc
└── sgi575

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: Iaccc86bc9d415f5c045c834902241fcf3c00277b

show more ...

refactor(sgi): move from "sgi" to "neoverse_rd"

Currently, reference design platforms such as RD-N2, RD-N1-Edge,
RD-V1-MC, RD-V1 and SGI-575 utilize "css/sgi" as the common source
directory. The "sg

refactor(sgi): move from "sgi" to "neoverse_rd"

Currently, reference design platforms such as RD-N2, RD-N1-Edge,
RD-V1-MC, RD-V1 and SGI-575 utilize "css/sgi" as the common source
directory. The "sgi" prefix originated from the System Guidance for
Infrastructure (SGI) and was initially associated with the SGI-575
platform. However, subsequent platforms released were under the Neoverse
Reference Design product name.

To align with the Neoverse Reference Design nomenclature, rename the
common source directory from "css/sgi" to "css/neoverse_rd" and update
all file prefixes from "sgi" to "nrd."

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: I3dcbb31b9ab202e82caf25218ba33c520dcea4e4

show more ...

feat(sgi): remove unused SGI_PLAT build-option

Currently, the common makefile has reference to "SGI_PLAT" build-option.
This however is not set by any of the platforms that makes use of the
common m

feat(sgi): remove unused SGI_PLAT build-option

Currently, the common makefile has reference to "SGI_PLAT" build-option.
This however is not set by any of the platforms that makes use of the
common makefile. Therefore, remove the unused SGI_PLAT build-option.

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: I6cc0b8d87222c7b3aef998774cee964a920cceb6

show more ...

fix(sgi): align to misra rule for braces

Misra rule states that braces have to be used with every 'if', 'else',
'for', 'do', and 'while' statement. In order to align with the said
rule, add braces f

fix(sgi): align to misra rule for braces

Misra rule states that braces have to be used with every 'if', 'else',
'for', 'do', and 'while' statement. In order to align with the said
rule, add braces for the statements within plat_css_get_scmi_info.

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: I826685e92926d90734b11d870dd624b11c9d1c30

show more ...

feat(rde1edge): remove support for RD-E1-Edge

As RD-E1_Edge is no longer actively supported and has been in the
deprecated list for a while, remove its support.

Signed-off-by: Rohit Mathew <Rohit.M

feat(rde1edge): remove support for RD-E1-Edge

As RD-E1_Edge is no longer actively supported and has been in the
deprecated list for a while, remove its support.

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: Iff66ad498dd99e44e2e6b79251ba2cbefbd5f3eb

show more ...

fix(rdn2): populate TOS_CONFIG only when SPMC_AT_EL3 is enabled

As of now, TOS_FW_CONFIG (trusted OS config) gets populated by default
for RD-N2. However, TOS_FW_CONFIG is required only when SPMC_AT

fix(rdn2): populate TOS_CONFIG only when SPMC_AT_EL3 is enabled

As of now, TOS_FW_CONFIG (trusted OS config) gets populated by default
for RD-N2. However, TOS_FW_CONFIG is required only when SPMC_AT_EL3 is
enabled. As the platform should support SPMC_AT_EL3 disabled mode as
well, populate TOS_CONFIG only when SPMC_AT_EL3 is enabled.
Additionally, building of rdn2_stmm_sel0_manifest.dtb is made
conditional to align with this configuration.

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: I9077d44b21d32ba7bf6b3b1c539662c14785ca6b

show more ...

fix(board): update spi_id max for sgi multichip platforms

According to GIC-600 TRM, 960 SPIs could be supported on a platform.
However, with the current configuration, platforms such as RD-V1-MC and

fix(board): update spi_id max for sgi multichip platforms

According to GIC-600 TRM, 960 SPIs could be supported on a platform.
However, with the current configuration, platforms such as RD-V1-MC and
RD-N1-Edge Dual-Chip utilize a much smaller range. With commit
'a02a45dfe' gic600 driver is updated to get the max SPI id from the
GIC-600 and probe for the corresponding GIC instance for each SPI id.
Since RD-V1-MC and RD-N1-Edge Dual-Chip supports wider range, increase
SPI range for the chip 0 to max SPI range supported.

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: Ia8c02c6d999033af33d8e7a0bedc7b73c6552ab4

show more ...

build(corstone1000): add CORSTONE1000_WITH_BL32 preprocessor flag

This change includes adding new CORSTONE1000_WITH_BL32 preprocessor
flag on the basis of NEED_BL32 flag. This flag allows us to run

build(corstone1000): add CORSTONE1000_WITH_BL32 preprocessor flag

This change includes adding new CORSTONE1000_WITH_BL32 preprocessor
flag on the basis of NEED_BL32 flag. This flag allows us to run the
TF-A with or without loading BL32 image. This feature is required to
add the support of Corstone-1000 FVP in TF-A open CI.
After this, we can run the TF-A tftf tests with or without
executing BL32 image, which is optee in case of Corstone-1000.

Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
Change-Id: Idacbd3883473473841481a2032314db8c9715b1f

show more ...

Merge "build: use toolchain identifiers in conditions" into integration

Merge "build: use new toolchain variables for tools" into integration

Merge "build: refactor toolchain detection" into integration

Merge "fix(imx8mp): uncondtionally enable only the USB power domain" into integration

feat(smmu): separate out smmuv3_security_init from smmuv3_init

Split the smmuv3_init() to separate smmuv3_security_init() from it in
order to allow skipping the default deny policy on reset for cert

feat(smmu): separate out smmuv3_security_init from smmuv3_init

Split the smmuv3_init() to separate smmuv3_security_init() from it in
order to allow skipping the default deny policy on reset for certain
SMMUv3 implementations.
Additionally, fix a couple of MISRA warnings.

Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Change-Id: I2127943e709dd1ded34145bd022c930e351bbb4a

show more ...

Merge "fix(bl2): make BL2 SRAM footprint flexible" into integration

Merge changes from topic "mb/tc-model-update" into integration

* changes:
docs: update FVP TC2 model version and build (11.23/17)
fix(tc): increase BL2 maximum size limit
refactor(tc): update

Merge changes from topic "mb/tc-model-update" into integration

* changes:
docs: update FVP TC2 model version and build (11.23/17)
fix(tc): increase BL2 maximum size limit
refactor(tc): update platform tests
feat(rss): add defines for 'type' range and use them in psa_call()
feat(rss): adjust parameter packing to match TF-M changes
refactor(tc): remap console logs

show more ...

fix(bl2): make BL2 SRAM footprint flexible

On FVP's the default SRAM size is severly restrictive. However, more
recent models support larger SRAM configurations (> 256 Kb). We
introduced the flag FV

fix(bl2): make BL2 SRAM footprint flexible

On FVP's the default SRAM size is severly restrictive. However, more
recent models support larger SRAM configurations (> 256 Kb). We
introduced the flag FVP_TRUSTED_SRAM_SIZE to allow for TF to handle
different configurations.

BL31 automatically benefits from this optimisation since it starts from
the bottom of shared memory, and runs up to the end of SRAM. Increase
the size of all BL2 builds in proportion to FVP_TRUSTED_SRAM_SIZE so
that BL2 covers around a third of SRAM.

Change-Id: Idf37e8cb86507ea44b97ac8b3b90fffefe13f57a
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

show more ...

fix(tc): increase BL2 maximum size limit

Increase the size of BL2 to build TC2 with GPT support enabled
and a config modification of mbedTLS.

Change-Id: I6d2f466144f2bbffd3387bc40bc86ab733febce1
Si

fix(tc): increase BL2 maximum size limit

Increase the size of BL2 to build TC2 with GPT support enabled
and a config modification of mbedTLS.

Change-Id: I6d2f466144f2bbffd3387bc40bc86ab733febce1
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

show more ...

refactor(tc): update platform tests

Update the TC's platform test Makefile and related common definitions
to correspond to newer TF-M code (commit hash: 4ab7a20).

Change-Id: I6ef3effe194a780a0533f9

refactor(tc): update platform tests

Update the TC's platform test Makefile and related common definitions
to correspond to newer TF-M code (commit hash: 4ab7a20).

Change-Id: I6ef3effe194a780a0533f9c0c2eab9d0f4efc1fc
Signed-off-by: David Vincze <david.vincze@arm.com>

show more ...

refactor(tc): remap console logs

Remap TF-A console logs from SoC UART2 (S1 terminal) to CSS
secure (UART1_AP terminal) and Linux logs from SoC UART2
(S1 terminal) to CSS non-secure (UART_AP termina

refactor(tc): remap console logs

Remap TF-A console logs from SoC UART2 (S1 terminal) to CSS
secure (UART1_AP terminal) and Linux logs from SoC UART2
(S1 terminal) to CSS non-secure (UART_AP terminal) to align
with the latest FVP TC2 model (version 11.23/17).

Change-Id: I7206e64b65346bfdcc48d6acd3792b436041e45f
Signed-off-by: Annam Sai Manisha <annam.saimanisha@arm.com>

show more ...