Merge "refactor(qemu): do not hardcode counter frequency" into integration

refactor(qemu): do not hardcode counter frequency

From QEMU change:

> In previous versions of the Arm architecture, the frequency of the
> generic timers as reported in CNTFRQ_EL0 could be any IMPD

refactor(qemu): do not hardcode counter frequency

From QEMU change:

> In previous versions of the Arm architecture, the frequency of the
> generic timers as reported in CNTFRQ_EL0 could be any IMPDEF value,
> and for QEMU we picked 62.5MHz, giving a timer tick period of 16ns.
> In Armv8.6, the architecture standardized this frequency to 1GHz.

This change stops TF-A from hardcoding 62.5MHz frequency. Instead value
stored in CNTFRQ_EL0 would be used. As a result we get 62.5MHz on older
cores and 1GHz on newer ones.

Change-Id: I7d414ce6d3708e598bbb5a6f79eb2d4ec8e15ac4
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

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refactor(fvp_r): remove duplicated macro definitions

The system counter macros are defined duplicatedly in the header file.
As the macros must be defined before arm_def.h, this patch removes the
red

refactor(fvp_r): remove duplicated macro definitions

The system counter macros are defined duplicatedly in the header file.
As the macros must be defined before arm_def.h, this patch removes the
redundant definitions afterwards.

Change-Id: Id74a8ef1b9cec4a978366b6db69981cfc30dffb6
Signed-off-by: Leo Yan <leo.yan@arm.com>

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refactor(qemu): change all occurrences of RSS to RSE

Changes all occurrences of "RSS" and "rss" in the code and build files
to "RSE" and "rse".

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-I

refactor(qemu): change all occurrences of RSS to RSE

Changes all occurrences of "RSS" and "rss" in the code and build files
to "RSE" and "rse".

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I2c6840f6f3f2f8f64595a0e0aa6e12084a37ce6e

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refactor(fvp): change all occurrences of RSS to RSE

Changes all occurrences of "RSS" and "rss" in the code and build files
to "RSE" and "rse".

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id

refactor(fvp): change all occurrences of RSS to RSE

Changes all occurrences of "RSS" and "rss" in the code and build files
to "RSE" and "rse".

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I36b8e498f3226fc72d21634aae2cc9328d00711d

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refactor(fvp): remove leftovers from rss measured boot support

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I1687327e028c2baec1ac6f0ae21b42b6047ceac0

refactor(tc): change all occurrences of RSS to RSE

Changes all occurrences of "RSS" and "rss" in the code and build files
to "RSE" and "rse".

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id:

refactor(tc): change all occurrences of RSS to RSE

Changes all occurrences of "RSS" and "rss" in the code and build files
to "RSE" and "rse".

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: Idec0bf7a90ae381f5bc968e1bb167daace24a11f

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refactor(tc): rename all 'rss' files to 'rse'

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I264690e9bbc30be7ed7b8e4e165696494a67e00c

fix(spm): add device-regions used in tf-a-tests

Device memory region specified in an SP manifest are now validated
against the device memory defined in the SPMC manifest. Therefore
we need to add th

fix(spm): add device-regions used in tf-a-tests

Device memory region specified in an SP manifest are now validated
against the device memory defined in the SPMC manifest. Therefore
we need to add the device memory used in the tf-a-tests to the SPMC
manifests.

Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
Change-Id: I47376e67c700705d12338d7078292618a15d5546

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fix(xilinx): check proc variable before use

Check return value from pm_get_proc() to make sure that CPU is valid.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: If51b5d42ce87f31fd732

fix(xilinx): check proc variable before use

Check return value from pm_get_proc() to make sure that CPU is valid.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: If51b5d42ce87f31fd732ab58ae8fcd0e2db0a2a8

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feat(qemu): allow ARM_ARCH_MAJOR/MINOR override

An upcoming change to the RME support code will use atomic instructions
introduced in Armv8.1 in order to implement bitlocks. In order to do
this, the

feat(qemu): allow ARM_ARCH_MAJOR/MINOR override

An upcoming change to the RME support code will use atomic instructions
introduced in Armv8.1 in order to implement bitlocks. In order to do
this, the code needs to be built with appropriate -march compiler flag
(otherwise the assembler complains about invalid instructions). One way
to do this is specifying ARM_ARCH_MAJOR/MINOR version greater than 8.0,
which is what the main Makefile does when ENABLE_RME is set.

Allow the main Makefile to override the ARM_ARCH_MAJOR/MINOR variables
on the QEMU platform, so that it can also build the bitlock functions.

This only affects firmware built with ENABLE_RME, which is an
experimental feature both in TF-A and QEMU. The QEMU platform code
doesn't support booting an ENABLE_RME firmware on non-RME CPUs at the
moment.

As a result of this change, when ENABLE_RME is set,
make_helpers/arch_features.mk sets ENABLE_TRF_FOR_NS to 1, which needs
to be overridden by the QEMU Makefile.

Change-Id: I695fc98b21d07f6c84003d9e36a57cad2a3c806e
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>

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fix: static checks on spmc dts

Change the header of the license to have 2024, and
replace spaces for a tab.

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: If98161ad35e1ead30e1e0d3ddb4cc6348

fix: static checks on spmc dts

Change the header of the license to have 2024, and
replace spaces for a tab.

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: If98161ad35e1ead30e1e0d3ddb4cc6348e83d6ee

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feat(intel): add QSPI get devinfo mailbox cmd

Linux RSU receive QSPI device info from SDM and report to user about
the device info.

Change-Id: Ib41692c9c4888c745a48a0609396aef0ca7fe25b
Signed-off-b

feat(intel): add QSPI get devinfo mailbox cmd

Linux RSU receive QSPI device info from SDM and report to user about
the device info.

Change-Id: Ib41692c9c4888c745a48a0609396aef0ca7fe25b
Signed-off-by: Kah Jing Lee <kah.jing.lee@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

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Merge changes from topic "lto-fixes" into integration

* changes:
fix(bl1): add missing `__RW_{START,END}__` symbols
fix(fvp): don't check MPIDRs with the power controller in BL1
fix(arm): only

Merge changes from topic "lto-fixes" into integration

* changes:
fix(bl1): add missing `__RW_{START,END}__` symbols
fix(fvp): don't check MPIDRs with the power controller in BL1
fix(arm): only expose `arm_bl2_dyn_cfg_init` to BL2
fix(cm): hide `cm_init_context_by_index` from BL1
fix(bl1): add missing spinlock dependency

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Merge changes from topic "hm/handoff" into integration

* changes:
refactor(fvp): reduce max size of HW_CONFIG to 16KB
refactor(arm): replace hard-coded HW_CONFIG DT size

feat(qemu): enable FEAT_ECV when present

QEMU supports FEAT_ECV since commit 2808d3b38a52 ("target/arm: Implement
FEAT_ECV CNTPOFF_EL2 handling"), in the v9.0.0 release. Enable
auto-detecting the fe

feat(qemu): enable FEAT_ECV when present

QEMU supports FEAT_ECV since commit 2808d3b38a52 ("target/arm: Implement
FEAT_ECV CNTPOFF_EL2 handling"), in the v9.0.0 release. Enable
auto-detecting the feature on the QEMU platforms, in order to set
SCR.ECVEN. Without this, EL2 gets undefined instruction exceptions when
trying to access the new CNTPOFF register.

Change-Id: I555a5f9a9a84fd23e64ca85219ed1599204c6bb2
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>

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Merge "fix(ff-a): add NS memory node to fvp_spmc_optee_sp manifest" into integration

refactor(fvp): reduce max size of HW_CONFIG to 16KB

HW_CONFIG is the hardware description consumed primarly by the Linux
kernel, and for the FVP platform, TF-A runtime firmware (BL31). Due to
both n

refactor(fvp): reduce max size of HW_CONFIG to 16KB

HW_CONFIG is the hardware description consumed primarly by the Linux
kernel, and for the FVP platform, TF-A runtime firmware (BL31). Due to
both needing it, two copies of this file are made in Trusted DRAM and
SRAM. The copy in Trusted DRAM is a workaround stemming from memory
constraints in SRAM. We temporarily map the range of memory in Trusted
DRAM into BL31 to allow it to consume the configuration. In principle,
however, BL31 execution should be limited to SRAM, hence reduce the
maximum size of the HW_CONFIG to 16KB in order to accommodate it in
SRAM. This is possible since in practice, the HW_CONFIG on FVP is only
about 11KB.

Change-Id: Idb5dc0637b402562b7177a2b4e2464c4f3f67da7
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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fix(intel): f2sdram bridge quick write thru failed

This patch is to fix the f2sdram bridge quick write thru failing by
removing the clear bit for sidebandmgr flagout register.

Change-Id: Ib03498fbb

fix(intel): f2sdram bridge quick write thru failed

This patch is to fix the f2sdram bridge quick write thru failing by
removing the clear bit for sidebandmgr flagout register.

Change-Id: Ib03498fbb2d91e9fd85f6315091ff72cbe3f394d
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

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refactor(arm): replace hard-coded HW_CONFIG DT size

Ensure consistency across all Arm platforms, even those that may already
have an existing macro for this purpose.

Change-Id: I07cd4cfcacf2c991717

refactor(arm): replace hard-coded HW_CONFIG DT size

Ensure consistency across all Arm platforms, even those that may already
have an existing macro for this purpose.

Change-Id: I07cd4cfcacf2c991717f4c115cb0babd2c614d6f
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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fix(fvp): don't check MPIDRs with the power controller in BL1

The core platform layer requires an implementation for the
`plat_core_pos_by_mpidr` function. This implementation is currently
missing i

fix(fvp): don't check MPIDRs with the power controller in BL1

The core platform layer requires an implementation for the
`plat_core_pos_by_mpidr` function. This implementation is currently
missing in BL1, which causes undefined reference errors when linking
with LTO.

The FVP platform source file providing this implementation is the
`fvp_topology.c` file, so this change adds it to the BL1 sources for the
FVP.

However, the implementation of this function reaches out to the FVP
power controller driver - `fvp_pm.c` - to validate the MPIDR, and this
file has at least two other dependencies:

- `spe.c`
- `arm_gicvX.c`

Pulling these in correctly is no simple job, so I am simply removing the
power controller validation in BL1 builds.

Change-Id: I56ddf1d799f5fe7f5b0fb2b046f7fe8232b07b27
Signed-off-by: Chris Kay <chris.kay@arm.com>

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fix(arm): only expose `arm_bl2_dyn_cfg_init` to BL2

The `arm_bl2_dyn_cfg_init` function is intended exclusively for BL2 - it
should not be compiled for any other bootloader image. This change hides

fix(arm): only expose `arm_bl2_dyn_cfg_init` to BL2

The `arm_bl2_dyn_cfg_init` function is intended exclusively for BL2 - it
should not be compiled for any other bootloader image. This change hides
it for all but BL2.

Change-Id: I9fa95094dcc30f9fa4cc7bc5b3119ceae82df1ea
Signed-off-by: Chris Kay <chris.kay@arm.com>

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feat(stm32mp2): add ddr-fw parameter for fiptool

When generating fiptool for STM32MP2, a new parameter is added to
put DDR firmware inside the FIP.

To avoid duplicating fiptool platform files, move

feat(stm32mp2): add ddr-fw parameter for fiptool

When generating fiptool for STM32MP2, a new parameter is added to
put DDR firmware inside the FIP.

To avoid duplicating fiptool platform files, move
tools/fiptool/plat_fiptool/st/stm32mp1 files in their parent directory
and move plat_def_fip_uuid.h in in plat/st/common/include.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I1dd796847869e2bfb6ee8c2bcef25c595fa5197a

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fix(ff-a): add NS memory node to fvp_spmc_optee_sp manifest

FFA_RXTX_MAP now requires the buffers to be in non-secure memory. This
patch ensures that a region of non-secure memory is available so th

fix(ff-a): add NS memory node to fvp_spmc_optee_sp manifest

FFA_RXTX_MAP now requires the buffers to be in non-secure memory. This
patch ensures that a region of non-secure memory is available so that
tftf tests can pass.

Change-Id: I9daf3182e0dcb73d2bf5a5baffb1b4b78c724dcb
Signed-off-by: Karl Meakin <karl.meakin@arm.com>

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Merge "refactor(arm): remove unused SP_MIN UART macros" into integration