feat(neoverse-rd): add CSS definitions for third gen platforms

Add CSS definitions for the third generation of reference design
platforms. Common definitions for such platforms would be housed in th

feat(neoverse-rd): add CSS definitions for third gen platforms

Add CSS definitions for the third generation of reference design
platforms. Common definitions for such platforms would be housed in the
nrd3 directory under includes.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Id271ebdf5dcc1d7b598606c313208ab85662795d

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feat(rockchip): add RK3566/RK3568 Socs support

RK3566/RK3568 is a Quad-core soc and Cortex-a55 inside.
This patch supports the following functions:
1. basic platform setup
2. power up/off cpus
3. su

feat(rockchip): add RK3566/RK3568 Socs support

RK3566/RK3568 is a Quad-core soc and Cortex-a55 inside.
This patch supports the following functions:
1. basic platform setup
2. power up/off cpus
3. suspend/resume cpus
4. suspend/resume system
5. reset system

Signed-off-by: shengfei Xu <xsf@rock-chips.com>
Change-Id: I8b98a4d07664de26bd6078f63664cbc3d9c1c68c

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fix(xilinx): handle power down event if SGI not registered

Currently, if SGI is not registered by Linux and power down event from
firmware is received then it's not getting handled in TF-A and core

fix(xilinx): handle power down event if SGI not registered

Currently, if SGI is not registered by Linux and power down event from
firmware is received then it's not getting handled in TF-A and core power
down is not happening. Because of that subsystem restart or force power
down without Linux boot is not happening. So, handle power down event in
TF-A if Linux not registered SGI.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I0c23792daba6ae47004ae99e232c77e17230bcfb

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fix(xilinx): register for idle callback

Currently, only Linux registering for getting idle callback during
subsystem restart or force power down. Because of that if Linux boot
hang or someone wants

fix(xilinx): register for idle callback

Currently, only Linux registering for getting idle callback during
subsystem restart or force power down. Because of that if Linux boot
hang or someone wants to do subsystem restart before Linux boot then
it's not working. So, register for idle callback in TF-A to get idle
callback during subsystem restart or force power down to do ARM
specific steps for proper power down of core.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: If7c01f79be6958678243be844bcfdc50d59b0fb8

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feat(xilinx): remove PM_IOCTL and PM_QUERY_DATA APIs

Today, the PM_IOCTL and PM_QUERY_DATA APIs are there to maintain
backward compatibility. Now, the usage of these APIs on the Linux
side and the f

feat(xilinx): remove PM_IOCTL and PM_QUERY_DATA APIs

Today, the PM_IOCTL and PM_QUERY_DATA APIs are there to maintain
backward compatibility. Now, the usage of these APIs on the Linux
side and the firmware side is updated. Hence remove the deprecated
PM_IOCTL and PM_QUERY_DATA EEMI API from the TF-A to make TF-A pass
through.

Note: Only use the newer kernel to access the deprecated features in
this patch. Otherwise, the system may not function correctly.

Change-Id: I23effb7ff62e7f83563c2b422ea64a0289fd880f
Signed-off-by: Ronak Jain <ronak.jain@amd.com>

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refactor(juno): add explicit entry for HW_CONFIG in BL2 CoT file

Add an explicit entry for HW_CONFIG in the BL2 CoT file for the Juno
platform, as the HW_CONFIG node has been removed from the common

refactor(juno): add explicit entry for HW_CONFIG in BL2 CoT file

Add an explicit entry for HW_CONFIG in the BL2 CoT file for the Juno
platform, as the HW_CONFIG node has been removed from the common CoT
file.

Change-Id: I8a1a22dd1023895cfc5730101fad20a80390ce17
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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refactor(fvp): add CoT desc dtsi

Adding CoT descriptor dtsi file to streamline fvp_tb_fw_config DTB file.

Change-Id: I0bbaef764b100ed0e749ec5f0c78a366398b3519
Signed-off-by: Lauren Wehrmeister <lau

refactor(fvp): add CoT desc dtsi

Adding CoT descriptor dtsi file to streamline fvp_tb_fw_config DTB file.

Change-Id: I0bbaef764b100ed0e749ec5f0c78a366398b3519
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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feat(arm): add COT_DESC_IN_DTB option for Dualroot

Add support for BL2 to get the Dualroot chain of trust description
through the Firmware Configuration Framework (FCONF). This makes it
possible to

feat(arm): add COT_DESC_IN_DTB option for Dualroot

Add support for BL2 to get the Dualroot chain of trust description
through the Firmware Configuration Framework (FCONF). This makes it
possible to export the part of the Dualroot chain of trust enforced by
BL2 in BL2's configuration file (TB_FW_CONFIG DTB file). BL2 will parse
it when setting up the platform.

The feature can be enabled through the COT_DESC_IN_DTB=1 option. The
default behavior (COT_DESC_IN_DTB=0) remains to hard-code the Dualroot
CoT into BL2 images.

Change-Id: I3497b1daf14be09b5ce3a74d39df7551819255c2
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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feat(fvp): add Dualroot CoT in DTB support

Adding support for Dualroot CoT in DTB. This makes it possible for BL2
to retrieve its chain of trust description from a configuration file in
DTB format.

feat(fvp): add Dualroot CoT in DTB support

Adding support for Dualroot CoT in DTB. This makes it possible for BL2
to retrieve its chain of trust description from a configuration file in
DTB format. With this, the CoT description may be updated without
rebuilding BL2 image.

This feature can be enabled by building BL2 with COT_DESC_IN_DTB=1 and
COT=dualroot. The default behavior remains to embed the CoT description
into BL2 image.

Change-Id: I343931b145aa8a53b0a5d4b8aefb273ffb5a9163
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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refactor(tc): append binding for SMMU-700

The usage for SMMU-700 is not consistent across TC platforms:

SMMU-700 on TC2:

| FVP | FPGA
--------+-------+------
Display | Used | Us

refactor(tc): append binding for SMMU-700

The usage for SMMU-700 is not consistent across TC platforms:

SMMU-700 on TC2:

| FVP | FPGA
--------+-------+------
Display | Used | Used
GPU | Used | Used

SMMU-700 on TC3:

| FVP | FPGA
--------+-------+------
Display | No | No
GPU | Used | No

This commit changes to use append mode for SMMU-700 to bind it on TC2
and TC3 separately. As a result, the TC_IOMMU_EN configuration is not
used, remove it.

Change-Id: Ic4152eb4c8ef97bf27b8a97c3c6cb86e32a2e8eb
Signed-off-by: Leo Yan <leo.yan@arm.com>

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feat(tc): configure MCN rdalloc and wralloc mode

SLC WRALLOCMODE and RDALLOCMODE are configured by default to 0b01
(always alloc), configure both to mode 0b10 (use bus signal attribute
from interfac

feat(tc): configure MCN rdalloc and wralloc mode

SLC WRALLOCMODE and RDALLOCMODE are configured by default to 0b01
(always alloc), configure both to mode 0b10 (use bus signal attribute
from interface).

Change-Id: Ic8cd3ee988dd0772cfb9b639dea0cc335ab70539
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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feat(tc): add dts entries for MCN PMU nodes

TC3 has 4 MCN instances, each of them have PMU registers to count
different MCN cache access events, add entries for MCN PMU so that Linux
MCN PMU perf dr

feat(tc): add dts entries for MCN PMU nodes

TC3 has 4 MCN instances, each of them have PMU registers to count
different MCN cache access events, add entries for MCN PMU so that Linux
MCN PMU perf driver can be used with perf.

Change-Id: I7e0ac5025231c3f19d5291292d4cae186accc544
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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feat(tc): enable MCN non-secure access to pmu counters on TC3

MCN PMU counters are by default non-accesible from non-secure world, so
enable the non-secure access to those PMU counters so that linux

feat(tc): enable MCN non-secure access to pmu counters on TC3

MCN PMU counters are by default non-accesible from non-secure world, so
enable the non-secure access to those PMU counters so that linux perf
driver can read them. FVP has a different address space size.

Change-Id: I2a3758faca5f7cab6d3146a1beb7b289eec0294d
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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Merge "feat(stm32mp15): remove OP-TEE shared mem" into integration

Merge "feat(tc): support full-HD resolution for the FVP model" into integration

Merge changes from topic "us_mhuv3" into integration

* changes:
feat(tc): add MHUv3 addresses between RSS and AP
feat(tc): specify MHU version based on platform
feat(tc): bind SCMI over MHUv3

Merge changes from topic "us_mhuv3" into integration

* changes:
feat(tc): add MHUv3 addresses between RSS and AP
feat(tc): specify MHU version based on platform
feat(tc): bind SCMI over MHUv3 for TC3
feat(tc): add MHUv3 DT binding for TC3
feat(tc): add MHUv3 doorbell support on TC3
refactor(tc): change tc_scmi_plat_info to single structure

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Merge changes from topic "gr/cpu_ren" into integration

* changes:
chore: rename Blackhawk to Cortex-X925
chore: rename Chaberton to Cortex-A725

chore: rename Blackhawk to Cortex-X925

Rename Blackhawk to Cortex-X925.

Change-Id: I51e40a7bc6b8871c53c40d1f341853b1fd7fdf71
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

fix(imx): disable DRAM retention by default on i.MX8MQ

Building the default upstream configuration for the imx8mq-evk is no longer
possible: The linker will complain that the TF-A image will no long

fix(imx): disable DRAM retention by default on i.MX8MQ

Building the default upstream configuration for the imx8mq-evk is no longer
possible: The linker will complain that the TF-A image will no longer
fit On-Chip SRAM.

In order to make the i.MX8MQ Image buildable again, let's make the DRAM
retention feature optional: It was added in v2.9 and it's possible to
boot the systems without it. Users that make space elsewhere and wish to
enable it can use the newly introduced IMX_DRAM_RETENTION parameter to
configure it. The parameter is added to all i.MX8M variants, but only
for i.MX8MQ, we disable it by default, as that's the one that currently
has binary size problems.

Change-Id: I714f8ea96f18154db02390ba500f4a2dc5329ee7
Fixes: dd108c3c1fe3 ("feat(imx8mq): add the dram retention support for imx8mq")
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>

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Merge "fix(imx8m): 8mq: enable imx_hab_handler" into integration

chore: rename Chaberton to Cortex-A725

Rename Chaberton to Cortex-A725.

Change-Id: I981b22d3b37f1aa6e25ff1f35aa156fff9c30076
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

fix(qemu): remove validate_ns_entrypoint

QEMU has dynamic memory configuration based on -m parameter. The
hard-coded values in TF-A are not accurate when starting the model with
this parameter. This

fix(qemu): remove validate_ns_entrypoint

QEMU has dynamic memory configuration based on -m parameter. The
hard-coded values in TF-A are not accurate when starting the model with
this parameter. This is not a problem when loading boot images as the
lower addresses are the same. However, it can be a problem when starting
up the secondary CPUs with a rather high non-secure entry point. So fix
this by removing the plat_psci_ops_t validate_ns_entrypoint assignment
to allow any non-secure entry point.

Change-Id: I95e92b71e0f4fa5f94444ea0cd2cb42e56faa472
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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Merge "fix(s32g274a): avoid overwriting const fields" into integration

Merge "feat(mt8188): update SVP region ID and permission" into integration

Merge changes I44537ba2,Ia12d3577,I06b3012c,Iec885405,Idab8013a into integration

* changes:
feat(imx8mp): optionally take params from BL2
feat(imx8mn): optionally take params from BL2
feat(imx

Merge changes I44537ba2,Ia12d3577,I06b3012c,Iec885405,Idab8013a into integration

* changes:
feat(imx8mp): optionally take params from BL2
feat(imx8mn): optionally take params from BL2
feat(imx8mm): optionally take params from BL2
feat(imx93): optionally take params from BL2
feat(imx): add helper to take params from BL2

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