refactor(tc): add platform specific DT files

Currently, the DT binding uses the file 'tc.dts' as a central place for
all TC platforms. And the variables (for different platforms, or FVP vs
FPGA, etc

refactor(tc): add platform specific DT files

Currently, the DT binding uses the file 'tc.dts' as a central place for
all TC platforms. And the variables (for different platforms, or FVP vs
FPGA, etc.) are maintained in 'tc_vers.dtsi'.

This patch renames 'tc.dts' to 'tc-base.dtsi' and creates an individual
.dts file for every platform. The purpose is to use 'tc-base.dtsi' for
maintaining common DT binding and every platform's specific definitions
will be moved into its own .dts file. This is a preparation for
sequential refactoring.

It changes to include the header files in platform DTS files but not in
the 'tc-base.dtsi'. This can allow 'tc-base.dtsi' is general enough and
platform DTS files covers platform specific defintions.

Change-Id: I034fb3f8836bcea36e8ad8ae01de41127693b0c6
Signed-off-by: Leo Yan <leo.yan@arm.com>

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fix(tc): enable FEAT_MTE2

Commit c282384db ("refactor(mte): remove mte, mte_perm") removes the
option FEAT_MTE and introduces FEAT_MTE2 option. Afterwards, the
FEAT_MTE2 option is missed on the TC p

fix(tc): enable FEAT_MTE2

Commit c282384db ("refactor(mte): remove mte, mte_perm") removes the
option FEAT_MTE and introduces FEAT_MTE2 option. Afterwards, the
FEAT_MTE2 option is missed on the TC platform and the feature is
disabled. As a result, it causes the panic in secure world.

This patch enables the FEAT_MTE2 option for TC platform to allow the
secure world can access the MTE registers properly.

Change-Id: If697236aa59bf4fb374e0ff43b53455ac2154e9c
Fixes: c282384db ("refactor(mte): remove mte, mte_perm")
Signed-off-by: Leo Yan <leo.yan@arm.com>

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build(rzg): separate BL2 and BL31 SREC generation

This small change creates individual Make non-phony targets for the Bl2
and BL31 SREC binaries to avoid rebuilding them unnecessarily.

Change-Id: I

build(rzg): separate BL2 and BL31 SREC generation

This small change creates individual Make non-phony targets for the Bl2
and BL31 SREC binaries to avoid rebuilding them unnecessarily.

Change-Id: Ia8e5db0e4a968d4b379fdb66123b6a8f20933bf5
Signed-off-by: Chris Kay <chris.kay@arm.com>

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build(rcar): separate BL2 and BL31 SREC generation

This small change creates individual Make non-phony targets for the Bl2
and BL31 SREC binaries to avoid rebuilding them unnecessarily.

Change-Id:

build(rcar): separate BL2 and BL31 SREC generation

This small change creates individual Make non-phony targets for the Bl2
and BL31 SREC binaries to avoid rebuilding them unnecessarily.

Change-Id: Ibb8880bb5c00a0956fc78d252fcc56391fbfe439
Signed-off-by: Chris Kay <chris.kay@arm.com>

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build: remove `MAKE_BUILD_STRINGS` function

This function causes the build message to be generated and compiled in
two different ways, with one way done inside `build_macros.mk` and the
other done i

build: remove `MAKE_BUILD_STRINGS` function

This function causes the build message to be generated and compiled in
two different ways, with one way done inside `build_macros.mk` and the
other done inside `windows.mk`, mostly because it's done by generating
the C file on the command line.

We can instead replace this whole build message generation sequence with
a simple standard C compilation command and a normal C file.

Change-Id: I8bc136380c9585ddeec9a11154ee39ef70526f81
Signed-off-by: Chris Kay <chris.kay@arm.com>

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feat(mt8188): remove apusys kernel handler usage constraints

It is expected that kernel can control the flow of the TF-A operations.
This patch remove the apusys kernel handler usage constraints, ma

feat(mt8188): remove apusys kernel handler usage constraints

It is expected that kernel can control the flow of the TF-A operations.
This patch remove the apusys kernel handler usage constraints, making
the operations all controlled on kernel side.

Signed-off-by: Karl Li <karl.li@mediatek.com>
Change-Id: Idc205a2cf23e1ff5f1920658a3b089c823f0288a

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fix(intel): add in watchdog for QSPI driver

ATF->Linux boot with QSPI boot source need to enable watchdog
so that it will not hang.

Change-Id: Id2a9ceebb1c89f711992a424f4394265efc6b388
Signed-off-b

fix(intel): add in watchdog for QSPI driver

ATF->Linux boot with QSPI boot source need to enable watchdog
so that it will not hang.

Change-Id: Id2a9ceebb1c89f711992a424f4394265efc6b388
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

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fix(tc): increase stack size when TRUSTED_BOARD_BOOT=0

The stack is too small for VERBOSE logging when secure world is disabled
as there is a recursive call when printing the translation table state

fix(tc): increase stack size when TRUSTED_BOARD_BOOT=0

The stack is too small for VERBOSE logging when secure world is disabled
as there is a recursive call when printing the translation table state
which causes a crash.

Changing the stack to the same value regardless of trusted boot.

Change-Id: I12298b33e47ae5206f74370262edce06b8a75d99
Signed-off-by: Alex Dobrescu <alex.dobrescu@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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Merge changes from topic "rss_rse_rename" into integration

* changes:
refactor(changelog): change all occurrences of RSS to RSE
refactor(qemu): change all occurrences of RSS to RSE
refactor(fv

Merge changes from topic "rss_rse_rename" into integration

* changes:
refactor(changelog): change all occurrences of RSS to RSE
refactor(qemu): change all occurrences of RSS to RSE
refactor(fvp): change all occurrences of RSS to RSE
refactor(fiptool): change all occurrences of RSS to RSE
refactor(psa): change all occurrences of RSS to RSE
refactor(fvp): remove leftovers from rss measured boot support
refactor(tc): change all occurrences of RSS to RSE
docs: change all occurrences of RSS to RSE
refactor(measured-boot): change all occurrences of RSS to RSE
refactor(rse): change all occurrences of RSS to RSE
refactor(psa): rename all 'rss' files to 'rse'
refactor(tc): rename all 'rss' files to 'rse'
docs: rename all 'rss' files to 'rse'
refactor(measured-boot): rename all 'rss' files to 'rse'
refactor(rss): rename all 'rss' files to 'rse'

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Merge changes from topic "hm/handoff" into integration

* changes:
feat(handoff): add support for RESET_TO_BL2
feat(arm): support FW handoff b/w BL1 & BL2
feat(handoff): add TL source files to

Merge changes from topic "hm/handoff" into integration

* changes:
feat(handoff): add support for RESET_TO_BL2
feat(arm): support FW handoff b/w BL1 & BL2
feat(handoff): add TL source files to BL1
feat(handoff): add TE's for BL1 handoff interface
refactor(bl1): clean up bl2 layout calculation
feat(arm): support FW handoff b/w BL2 & BL31

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feat(imx8mp): optionally take params from BL2

Optionally take params from BL2 to offer more flexibility to BL2 on
where and if a BL32 image is expected. This uses imx_bl31_params_parse()
to check if

feat(imx8mp): optionally take params from BL2

Optionally take params from BL2 to offer more flexibility to BL2 on
where and if a BL32 image is expected. This uses imx_bl31_params_parse()
to check if arg0 can safely be accessed as a pointer and actually
contains a bl_params_t structure. If not, the hardcoded parameter
values are used as before.

Change-Id: I44537ba2baa7543e459e5691b69df14b0bd6e942
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

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feat(imx8mn): optionally take params from BL2

Optionally take params from BL2 to offer more flexibility to BL2 on
where and if a BL32 image is expected. This uses imx_bl31_params_parse()
to check if

feat(imx8mn): optionally take params from BL2

Optionally take params from BL2 to offer more flexibility to BL2 on
where and if a BL32 image is expected. This uses imx_bl31_params_parse()
to check if arg0 can safely be accessed as a pointer and actually
contains a bl_params_t structure. If not, the hardcoded parameter
values are used as before.

Change-Id: Ia12d35778f4d550860e517f2a1f5c5d062f3283a
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

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feat(imx8mm): optionally take params from BL2

Optionally take params from BL2 to offer more flexibility to BL2 on
where and if a BL32 image is expected. This uses imx_bl31_params_parse()
to check if

feat(imx8mm): optionally take params from BL2

Optionally take params from BL2 to offer more flexibility to BL2 on
where and if a BL32 image is expected. This uses imx_bl31_params_parse()
to check if arg0 can safely be accessed as a pointer and actually
contains a bl_params_t structure. If not, the hardcoded parameter
values are used as before.

Change-Id: I06b3012c67e43ea1e42946d863226bd93ccd4638
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

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feat(imx93): optionally take params from BL2

Optionally take params from BL2 to offer more flexibility to BL2 on
where and if a BL32 image is expected. This uses imx_bl31_params_parse()
to check if

feat(imx93): optionally take params from BL2

Optionally take params from BL2 to offer more flexibility to BL2 on
where and if a BL32 image is expected. This uses imx_bl31_params_parse()
to check if arg0 can safely be accessed as a pointer and actually
contains a bl_params_t structure. If not, the hardcoded parameter
values are used as before.

Change-Id: Iec885405efd31a6bf6c0e6c532f8d2f31c023333
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

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feat(imx): add helper to take params from BL2

So far the i.MX BL31 doesn't take any parameters. This means the BL32
image base address and whether or not a BL32 image is used at all has to
be hardco

feat(imx): add helper to take params from BL2

So far the i.MX BL31 doesn't take any parameters. This means the BL32
image base address and whether or not a BL32 image is used at all has to
be hardcoded in BL31.

This adds a helper function that allows to take params from BL2 safely.
On i.MX BL2 is usually U-Boot SPL which passes random values in arg0,
so make sure arg0 is within the internal SRAM range before accessing it
as a pointer. Also make sure arg0 is sufficiently aligned and the header
type and version is correct.

Change-Id: Idab8013a1d6dabf50a83c75f3e6f831de4a537e9
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

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feat(handoff): add support for RESET_TO_BL2

When BL2 is enabled as the entrypoint in the reset vector, none of the
TL initialisation ordinarily performed in BL1 will have been done. This
change ensu

feat(handoff): add support for RESET_TO_BL2

When BL2 is enabled as the entrypoint in the reset vector, none of the
TL initialisation ordinarily performed in BL1 will have been done. This
change ensures that BL2 has a secure TL to pass information onto BL31
through.

Change-Id: I553b0b7aac9390cd6a2d63471b81ddc72cc40a60
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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feat(arm): support FW handoff b/w BL1 & BL2

Leverage the framework between BL1 and BL2. Migrate all handoff
structures to the TL.

Change-Id: I79ff3a319596b5656184cde10b5204b10a4d03bb
Signed-off-by:

feat(arm): support FW handoff b/w BL1 & BL2

Leverage the framework between BL1 and BL2. Migrate all handoff
structures to the TL.

Change-Id: I79ff3a319596b5656184cde10b5204b10a4d03bb
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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refactor(bl1): clean up bl2 layout calculation

Layout calculation is spread out between core BL1 logic and common
platform code. Relocate these into common platform code so they are
organised logica

refactor(bl1): clean up bl2 layout calculation

Layout calculation is spread out between core BL1 logic and common
platform code. Relocate these into common platform code so they are
organised logically.

Change-Id: I8b05403e41b800957a0367316cecd373d10bb1a4
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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feat(arm): support FW handoff b/w BL2 & BL31

Add support for the firmware handoff framework between BL2 and BL31.
Create a transfer list in trusted SRAM, leveraging the larger SRAM sizes
in recent m

feat(arm): support FW handoff b/w BL2 & BL31

Add support for the firmware handoff framework between BL2 and BL31.
Create a transfer list in trusted SRAM, leveraging the larger SRAM sizes
in recent models. Load the HW_CONFIG as a TE along with entry point
parameters for BL31 execution.

Change-Id: I7c4c6e8353ca978a13520fb3e15fb2803f0f1d0e
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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Merge "fix(tc): missing device regions in spmc manifest" into integration

fix(tc): missing device regions in spmc manifest

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: I847c9ec13c3d40dd9de8cf374a81fc6d23a8864c

feat(s32g274a): enable BL31 stage

Add BL31 prerequisites for the S32G274ARDB2 board to allow single-core
cold boot without MMU and PSCI services.

Change-Id: I8a10fd62f3cc9430083758043ea82e3803f6106

feat(s32g274a): enable BL31 stage

Add BL31 prerequisites for the S32G274ARDB2 board to allow single-core
cold boot without MMU and PSCI services.

Change-Id: I8a10fd62f3cc9430083758043ea82e3803f61060
Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@nxp.com>
Signed-off-by: Bogdan Roman <bogdan-gabriel.roman@nxp.com>
Signed-off-by: Andra-Teodora Ilie <andra.ilie@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(s32g274a): add S32G274ARDB2 board support

S32G274ARDB2 is a development board to showcase the capabilities of the
S32G2 SoC. It includes 4 ARM Cortex-A53 cores running at 1.0GHz, 4GBs
of DDR, a

feat(s32g274a): add S32G274ARDB2 board support

S32G274ARDB2 is a development board to showcase the capabilities of the
S32G2 SoC. It includes 4 ARM Cortex-A53 cores running at 1.0GHz, 4GBs
of DDR, accelerators for automotive networking and many other
peripherals.

The added support is minimal and only includes the BL2 stage, with no
MMU enabled. The FIP is preloaded by the BootROM in SRAM, and BL2 copies
BL31 and BL33 from FIP to their designated addresses.

Change-Id: Iedda23302768ab70d63787117c5f6f3c21eb9842
Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@nxp.com>
Signed-off-by: Dan Nica <dan.nica@nxp.com>
Signed-off-by: Andra-Teodora Ilie <andra.ilie@nxp.com>
Signed-off-by: Bogdan Roman <bogdan-gabriel.roman@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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refactor(neoverse-rd): remove soc_css.mk from common makefile

The soc_css.mk file within the plat/arm/soc module currently implements
initialization functions for the PCIe controller and NIC400 with

refactor(neoverse-rd): remove soc_css.mk from common makefile

The soc_css.mk file within the plat/arm/soc module currently implements
initialization functions for the PCIe controller and NIC400 within the
SOC specification. However, as none of the Neoverse reference design
platforms necessitate the initialization of PCIe or NIC400, remove the
soc_css.mk from the common makefile.

Additionally, empty initialization functions for PCIe and NIC400 are
added to satisfy the requirements of the plat/arm common code, which
expects these functions to be present.

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: Ia431af62f48fc224962d64902dd3acfbf0b93935

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refactor(neoverse-rd): unify GIC SPI range macros

The existing macros representing GIC SPI minimum and maximum for
multichip platforms lack a consistent naming convention. To address
this, establish

refactor(neoverse-rd): unify GIC SPI range macros

The existing macros representing GIC SPI minimum and maximum for
multichip platforms lack a consistent naming convention. To address
this, establish the convention "NRD_CHIP<x>_SPI_MIN" and
"NRD_CHIP<x>_SPI_MAX" for use across all Neoverse Reference Design
multichip platforms.

Furthermore, extend this naming convention to RD-N2-Cfg2 and introduce
similar macros.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Idca2a8c66579f05e712e3b6e95204fedc122cf23

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