feat(arm): add COT_DESC_IN_DTB option for Dualroot

Add support for BL2 to get the Dualroot chain of trust description
through the Firmware Configuration Framework (FCONF). This makes it
possible to

feat(arm): add COT_DESC_IN_DTB option for Dualroot

Add support for BL2 to get the Dualroot chain of trust description
through the Firmware Configuration Framework (FCONF). This makes it
possible to export the part of the Dualroot chain of trust enforced by
BL2 in BL2's configuration file (TB_FW_CONFIG DTB file). BL2 will parse
it when setting up the platform.

The feature can be enabled through the COT_DESC_IN_DTB=1 option. The
default behavior (COT_DESC_IN_DTB=0) remains to hard-code the Dualroot
CoT into BL2 images.

Change-Id: I3497b1daf14be09b5ce3a74d39df7551819255c2
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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feat(fvp): add Dualroot CoT in DTB support

Adding support for Dualroot CoT in DTB. This makes it possible for BL2
to retrieve its chain of trust description from a configuration file in
DTB format.

feat(fvp): add Dualroot CoT in DTB support

Adding support for Dualroot CoT in DTB. This makes it possible for BL2
to retrieve its chain of trust description from a configuration file in
DTB format. With this, the CoT description may be updated without
rebuilding BL2 image.

This feature can be enabled by building BL2 with COT_DESC_IN_DTB=1 and
COT=dualroot. The default behavior remains to embed the CoT description
into BL2 image.

Change-Id: I343931b145aa8a53b0a5d4b8aefb273ffb5a9163
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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refactor(tc): append binding for SMMU-700

The usage for SMMU-700 is not consistent across TC platforms:

SMMU-700 on TC2:

| FVP | FPGA
--------+-------+------
Display | Used | Us

refactor(tc): append binding for SMMU-700

The usage for SMMU-700 is not consistent across TC platforms:

SMMU-700 on TC2:

| FVP | FPGA
--------+-------+------
Display | Used | Used
GPU | Used | Used

SMMU-700 on TC3:

| FVP | FPGA
--------+-------+------
Display | No | No
GPU | Used | No

This commit changes to use append mode for SMMU-700 to bind it on TC2
and TC3 separately. As a result, the TC_IOMMU_EN configuration is not
used, remove it.

Change-Id: Ic4152eb4c8ef97bf27b8a97c3c6cb86e32a2e8eb
Signed-off-by: Leo Yan <leo.yan@arm.com>

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feat(tc): configure MCN rdalloc and wralloc mode

SLC WRALLOCMODE and RDALLOCMODE are configured by default to 0b01
(always alloc), configure both to mode 0b10 (use bus signal attribute
from interfac

feat(tc): configure MCN rdalloc and wralloc mode

SLC WRALLOCMODE and RDALLOCMODE are configured by default to 0b01
(always alloc), configure both to mode 0b10 (use bus signal attribute
from interface).

Change-Id: Ic8cd3ee988dd0772cfb9b639dea0cc335ab70539
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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feat(tc): add dts entries for MCN PMU nodes

TC3 has 4 MCN instances, each of them have PMU registers to count
different MCN cache access events, add entries for MCN PMU so that Linux
MCN PMU perf dr

feat(tc): add dts entries for MCN PMU nodes

TC3 has 4 MCN instances, each of them have PMU registers to count
different MCN cache access events, add entries for MCN PMU so that Linux
MCN PMU perf driver can be used with perf.

Change-Id: I7e0ac5025231c3f19d5291292d4cae186accc544
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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feat(tc): enable MCN non-secure access to pmu counters on TC3

MCN PMU counters are by default non-accesible from non-secure world, so
enable the non-secure access to those PMU counters so that linux

feat(tc): enable MCN non-secure access to pmu counters on TC3

MCN PMU counters are by default non-accesible from non-secure world, so
enable the non-secure access to those PMU counters so that linux perf
driver can read them. FVP has a different address space size.

Change-Id: I2a3758faca5f7cab6d3146a1beb7b289eec0294d
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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Merge "feat(stm32mp15): remove OP-TEE shared mem" into integration

Merge "feat(tc): support full-HD resolution for the FVP model" into integration

Merge changes from topic "us_mhuv3" into integration

* changes:
feat(tc): add MHUv3 addresses between RSS and AP
feat(tc): specify MHU version based on platform
feat(tc): bind SCMI over MHUv3

Merge changes from topic "us_mhuv3" into integration

* changes:
feat(tc): add MHUv3 addresses between RSS and AP
feat(tc): specify MHU version based on platform
feat(tc): bind SCMI over MHUv3 for TC3
feat(tc): add MHUv3 DT binding for TC3
feat(tc): add MHUv3 doorbell support on TC3
refactor(tc): change tc_scmi_plat_info to single structure

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Merge changes from topic "gr/cpu_ren" into integration

* changes:
chore: rename Blackhawk to Cortex-X925
chore: rename Chaberton to Cortex-A725

chore: rename Blackhawk to Cortex-X925

Rename Blackhawk to Cortex-X925.

Change-Id: I51e40a7bc6b8871c53c40d1f341853b1fd7fdf71
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

fix(imx): disable DRAM retention by default on i.MX8MQ

Building the default upstream configuration for the imx8mq-evk is no longer
possible: The linker will complain that the TF-A image will no long

fix(imx): disable DRAM retention by default on i.MX8MQ

Building the default upstream configuration for the imx8mq-evk is no longer
possible: The linker will complain that the TF-A image will no longer
fit On-Chip SRAM.

In order to make the i.MX8MQ Image buildable again, let's make the DRAM
retention feature optional: It was added in v2.9 and it's possible to
boot the systems without it. Users that make space elsewhere and wish to
enable it can use the newly introduced IMX_DRAM_RETENTION parameter to
configure it. The parameter is added to all i.MX8M variants, but only
for i.MX8MQ, we disable it by default, as that's the one that currently
has binary size problems.

Change-Id: I714f8ea96f18154db02390ba500f4a2dc5329ee7
Fixes: dd108c3c1fe3 ("feat(imx8mq): add the dram retention support for imx8mq")
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>

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Merge "fix(imx8m): 8mq: enable imx_hab_handler" into integration

chore: rename Chaberton to Cortex-A725

Rename Chaberton to Cortex-A725.

Change-Id: I981b22d3b37f1aa6e25ff1f35aa156fff9c30076
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

fix(qemu): remove validate_ns_entrypoint

QEMU has dynamic memory configuration based on -m parameter. The
hard-coded values in TF-A are not accurate when starting the model with
this parameter. This

fix(qemu): remove validate_ns_entrypoint

QEMU has dynamic memory configuration based on -m parameter. The
hard-coded values in TF-A are not accurate when starting the model with
this parameter. This is not a problem when loading boot images as the
lower addresses are the same. However, it can be a problem when starting
up the secondary CPUs with a rather high non-secure entry point. So fix
this by removing the plat_psci_ops_t validate_ns_entrypoint assignment
to allow any non-secure entry point.

Change-Id: I95e92b71e0f4fa5f94444ea0cd2cb42e56faa472
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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Merge "fix(s32g274a): avoid overwriting const fields" into integration

Merge "feat(mt8188): update SVP region ID and permission" into integration

Merge changes I44537ba2,Ia12d3577,I06b3012c,Iec885405,Idab8013a into integration

* changes:
feat(imx8mp): optionally take params from BL2
feat(imx8mn): optionally take params from BL2
feat(imx

Merge changes I44537ba2,Ia12d3577,I06b3012c,Iec885405,Idab8013a into integration

* changes:
feat(imx8mp): optionally take params from BL2
feat(imx8mn): optionally take params from BL2
feat(imx8mm): optionally take params from BL2
feat(imx93): optionally take params from BL2
feat(imx): add helper to take params from BL2

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Merge changes I710d1780,Ia9a59bde into integration

* changes:
feat(gpt): configure memory size protected by bitlock
feat(gpt): add support for large GPT mappings

feat(mt8188): update SVP region ID and permission

- Update SVP EMI-MPU region ID from 4 to 5 for resolving
the issue of duplicate region ID used by the DSP.
- For SVP EMI-MPU region, modify domain

feat(mt8188): update SVP region ID and permission

- Update SVP EMI-MPU region ID from 4 to 5 for resolving
the issue of duplicate region ID used by the DSP.
- For SVP EMI-MPU region, modify domain 1 and domain 6 APC from
FORBIDDEN to SEC_RW.
- Correct the calculation for the end address of SVP DRAM region.
- Add region 0 and region 1 for BL31 and BL32 memory protection.
- Add clear region protection API for SVP region.

Change-Id: Iaea348ad9be629e8a81cf579b148c6df66015b42
Signed-off-by: Haohao Sun <haohao.sun@mediatek.corp-partner.google.com>

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feat(mt8188): update the memory usage for SCP core0 and core1

- Reduce core0 memory usage from 41MB to 8MB.
- Increase core1 memory to 160MB to fulfill user-specific features.

Change-Id: I35547e2ac

feat(mt8188): update the memory usage for SCP core0 and core1

- Reduce core0 memory usage from 41MB to 8MB.
- Increase core1 memory to 160MB to fulfill user-specific features.

Change-Id: I35547e2ac928945c244883d2333f921ce578bbd1
Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com>

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feat(stm32mp15): remove OP-TEE shared mem

The flag STM32MP15_OPTEE_RSV_SHM was disabled and mark deprecated.
Remove the corresponding code.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-

feat(stm32mp15): remove OP-TEE shared mem

The flag STM32MP15_OPTEE_RSV_SHM was disabled and mark deprecated.
Remove the corresponding code.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I948af3e1de4b89815c967a63abe64f285c405ecc

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refactor(qemu): use the example CCA platform token from iat-verifier

In [1], the example CCA platform token has been updated to fix a small
problem with the description of one of the software compon

refactor(qemu): use the example CCA platform token from iat-verifier

In [1], the example CCA platform token has been updated to fix a small
problem with the description of one of the software components, and to
provide a more realistic breakdown of the expected components in the CCA
TCB.

This change replaces the static CCA platform token in QEMU.

[1] https://review.trustedfirmware.org/c/TF-M/tf-m-tools/+/28493

Change-Id: I8ce49e6ecf83c426dee9024e782a8da457316959
Signed-off-by: Thomas Fossati <thomas.fossati@linaro.org>

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feat(tc): support full-HD resolution for the FVP model

Enable full-HD resolution (1920x1080p60) for the FVP model, and add
checking for the passed resolution parameter.

Change-Id: I5e37ae79b5ceac08

feat(tc): support full-HD resolution for the FVP model

Enable full-HD resolution (1920x1080p60) for the FVP model, and add
checking for the passed resolution parameter.

Change-Id: I5e37ae79b5ceac088a18d5acf00ff4a557bb56aa
Signed-off-by: Sergio Alves <sergio.dasilvalves@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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feat(tc): add MHUv3 addresses between RSS and AP

TC3 is upgraded to MHUv3. This patch adds the address of the MHU
channel to be used by TF-A for communications with the RSS.

Change-Id: I1bf5d72dc92

feat(tc): add MHUv3 addresses between RSS and AP

TC3 is upgraded to MHUv3. This patch adds the address of the MHU
channel to be used by TF-A for communications with the RSS.

Change-Id: I1bf5d72dc92bcd9d0509ba806095b24293875e85
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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