feat(fpga): enable new CPU features

Newer cores implemented in the FPGAs used by Arm Ltd. support more
ARMv9 features.

Enable TCR2, MTE, MTE2, SME and SME2 as "enable if available" (:=2), so
any us

feat(fpga): enable new CPU features

Newer cores implemented in the FPGAs used by Arm Ltd. support more
ARMv9 features.

Enable TCR2, MTE, MTE2, SME and SME2 as "enable if available" (:=2), so
any users of those features in lower ELs will not trigger a trap into
BL31.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: Id99ecb7c5d6a25b77f7cc5fcad63f60027a4fd5a

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refactor(st): change method to get GIC base addresses

GIC DT node structure depends on system architecture, notably around
"reg" property. A generic way to retrieve base address is needed. Use
fdt_n

refactor(st): change method to get GIC base addresses

GIC DT node structure depends on system architecture, notably around
"reg" property. A generic way to retrieve base address is needed. Use
fdt_node_offset_by_compatible() helper.

Change-Id: Ibb47864bd5e8a76a48b9346fdcf87d31281517ce
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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Merge "fix(fpga): avoid stripping kernel trampoline" into integration

Merge changes from topic "rockchip" into integration

* changes:
fix(rockchip): add parenthesis for BITS_SHIFT macro
fix(rockchip): xlat: fix compatibility between v1 and v2

feat(mediatek): configure DEV_IRQ as G1S interrupt

In order to register DEV_IRQ as secure interrupt in OP-TEE, the the GICD
EnableGrp1S should be enabled for DEV_IRQ. Add mtk_interrupt_props in
MTK

feat(mediatek): configure DEV_IRQ as G1S interrupt

In order to register DEV_IRQ as secure interrupt in OP-TEE, the the GICD
EnableGrp1S should be enabled for DEV_IRQ. Add mtk_interrupt_props in
MTK GIC driver to configure the interrupt properly.

Signed-off-by: Gavin Liu <gavin.liu@mediatek.com>
Change-Id: Id909a42b535088c6d0dcaf803d3f2faf312ae846

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fix(fpga): avoid stripping kernel trampoline

The Arm FPGA platform builds a final AXF file, which is an ELF file
containing some required trampolines and binaries, like the DTB. This is
more a "cont

fix(fpga): avoid stripping kernel trampoline

The Arm FPGA platform builds a final AXF file, which is an ELF file
containing some required trampolines and binaries, like the DTB. This is
more a "container with load addresses" than an object or executable
file, but it's still built with the linker tool.
Commit acf0076ae2e5 ("build(fpga): correctly handle gcc as linker for
LTO") pulled in ${TF_LDFLAGS} when building this AXF file, which
includes "--gc-sections". That strips the kernel trampoline off that
file, making the board hang when the kernel is loaded at 0x80200000
(the recommended load address for "newer" kernels).

Drop the usage of TF_LDFLAGS altogether, since we need none of the
options specified there for our special linker step. Instead collect
the needed options (like -nostdlib) in a separate variable, and just
account for the slight syntax differences between GCC and clang.
"--strip-debug" turns out to be redundant, since "-s" already strips
more symbols, so remove that from the list.

Change-Id: I1349d58fa93973ba3add8cab2272259abdea84e0
Fixes: acf0076ae2e5 ("build(fpga): correctly handle gcc as linker for LTO")
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge changes from topic "st-fwu-common" into integration

* changes:
refactor(st): move FWU support to common code
refactor(st): move FWU functions to common code

Merge "feat(corstone1000): add multicore support for fvp" into integration

Merge "refactor(dice): save parent context handle" into integration

feat(tc): add uart node in spmc manifest

The device memory described in the SP manifest has to be described in
the SPMC manifest as well. In this case, OP-TEE includes this UART
device in its SP man

feat(tc): add uart node in spmc manifest

The device memory described in the SP manifest has to be described in
the SPMC manifest as well. In this case, OP-TEE includes this UART
device in its SP manifest. Hence, this commit adds it in the SPMC
manifest.

Change-Id: I0f84d7b105c072dd021f0f2d215adf6bcdf5f98f
Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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Merge "feat(versal2): add support for AMD Versal Gen 2 platform" into integration

Merge changes from topic "ip_smmu" into integration

* changes:
feat(tc): bind SMMU-600 with the DPU on TC3 FPGA
feat(tc): bind SMMU-700 with DPU on TC3
refactor(tc): append binding for SMMU-700

Merge "feat(versal-net): set lower cluster bus qos value" into integration

feat(corstone1000): add multicore support for fvp

This changeset adds the multicore support for the Corstone-1000 FVP.
It adds the PSCI CPU_ON and CPU_ON_FINISH power domain functionalities
for the

feat(corstone1000): add multicore support for fvp

This changeset adds the multicore support for the Corstone-1000 FVP.
It adds the PSCI CPU_ON and CPU_ON_FINISH power domain functionalities
for the secondary cores.

Change-Id: Ie66b3dc43abadec88323999052357e2a9cdfd950
Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>

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refactor(st): move FWU support to common code

Move PLAT_PARTITION_MAX_ENTRIES and all other definitions linked to it
to common.mk.
Move drivers/fwu/fwu.mk inclusion there as well.

Signed-off-by: Ya

refactor(st): move FWU support to common code

Move PLAT_PARTITION_MAX_ENTRIES and all other definitions linked to it
to common.mk.
Move drivers/fwu/fwu.mk inclusion there as well.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I5dde65e41908d706328cb8929582f827ceeff841

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refactor(st): move FWU functions to common code

Move the platforms functions used for Firmware update in plat/st/common
directory. The function stm32mp1_fwu_set_boot_idx() is renamed
stm32_fwu_set_b

refactor(st): move FWU functions to common code

Move the platforms functions used for Firmware update in plat/st/common
directory. The function stm32mp1_fwu_set_boot_idx() is renamed
stm32_fwu_set_boot_idx() to align with other ones. A new function
stm32_get_bkpr_fwu_info_addr() is created to get the backup register
address where to store FWU info (counter and partition index).

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I64916c7992782ceeaaf990026756ca4134d93c88

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feat(versal-net): set lower cluster bus qos value

arm clusterbusqos register has a default value of 0xeeeeeeee.
this may create bottleneck for other masters in system when
accessing other memories i

feat(versal-net): set lower cluster bus qos value

arm clusterbusqos register has a default value of 0xeeeeeeee.
this may create bottleneck for other masters in system when
accessing other memories including ddr.
hence clusterbusqos is setup to lowest value 0.

Change-Id: I73d55066eb84e198c8c69593bb5700745f04f290
Signed-off-by: Amit Nagal <amit.nagal@amd.com>

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Merge "feat(fvp): add cpu power control" into integration

Merge changes from topic "st-nand-backup-fwu" into integration

* changes:
refactor(st): rename plat_set_image_source
feat(st): add FWU with boot from NAND
feat(st): manage backup partitions fo

Merge changes from topic "st-nand-backup-fwu" into integration

* changes:
refactor(st): rename plat_set_image_source
feat(st): add FWU with boot from NAND
feat(st): manage backup partitions for NAND devices
feat(bl): add plat handler for image loading
refactor(bl)!: remove unused plat_try_next_boot_source

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refactor(tc): use the example CCA platform token from iat-verifier

In [1], the example CCA platform token has been updated to fix a small
problem with the description of one of the software componen

refactor(tc): use the example CCA platform token from iat-verifier

In [1], the example CCA platform token has been updated to fix a small
problem with the description of one of the software components, and to
provide a more realistic breakdown of the expected components in the CCA
TCB.

This change replaces the static CCA platform token in the Total Compute
platform.

[1] https://review.trustedfirmware.org/c/TF-M/tf-m-tools/+/28493

Change-Id: I792e693cc994fc1e856f713fd97bac4930b28e1e
Signed-off-by: Thomas Fossati <thomas.fossati@linaro.org>

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Merge changes from topic "st_gpio_update" into integration

* changes:
fix(st-gpio): configure each GPIO mux as secure for STM32MP2
feat(st-gpio): add set GPIO config API
fix(stm32mp1): remove

Merge changes from topic "st_gpio_update" into integration

* changes:
fix(st-gpio): configure each GPIO mux as secure for STM32MP2
feat(st-gpio): add set GPIO config API
fix(stm32mp1): remove unnecessary assert on GPIO_BANK_A value
refactor(st): use GPIO banks definition from bindings
feat(dt-bindings): describe ST GPIO banks and config

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Merge "fix(tc): add SCP_BL2 to RSE measured boot" into integration

fix(stm32mp1): remove unnecessary assert on GPIO_BANK_A value

Remove assert for unexpected value of the define GPIO_BANK_A.

This check is not required as GPIO_BANK_A = 0, it can be limited to
have

fix(stm32mp1): remove unnecessary assert on GPIO_BANK_A value

Remove assert for unexpected value of the define GPIO_BANK_A.

This check is not required as GPIO_BANK_A = 0, it can be limited to
have bank <= GPIO_BANK_K as bank is unsigned int.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I0345d56f106fcacd6a6f93281c2d9279980cd152

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refactor(st): use GPIO banks definition from bindings

Use GPIO banks definition from bindings.

Change-Id: I4dcf321345e319af78285e940b72a1369569b996
Signed-off-by: Pascal Paillet <p.paillet@st.com>

fix(qemu): allocate space for GPT bitlock

Since commit ec0088bbab93 ("feat(gpt): add support for large GPT
mappings"), the platform needs to reserve space for the bitlock,
immediately after the L0 G

fix(qemu): allocate space for GPT bitlock

Since commit ec0088bbab93 ("feat(gpt): add support for large GPT
mappings"), the platform needs to reserve space for the bitlock,
immediately after the L0 GPT table. Add two pages to the L0 GPT reserve.
This could be optimized later by moving the bitlock somewhere else,
because it really only needs (1 << PPS.T) / (512M * 8) = 256 bytes for
the QEMU virt platform.

Fix two more comments in qemu_pas_def.h since we're here.

Change-Id: I2b0b8de38f4b5058735ed16f1cdc50e6b2d52ad9
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>

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