refactor(tc): rename DPE header

The new name is more generic. The goal to add here
all platform dependent defines / data / config which
is DPE related.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>

refactor(tc): rename DPE header

The new name is more generic. The goal to add here
all platform dependent defines / data / config which
is DPE related.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I5b521932c45d8a9c43ea2344dde83c210801cfee

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Merge "refactor(tc): use the example CCA platform token from iat-verifier" into integration

Merge "feat(tc): add uart node in spmc manifest" into integration

fix(tc): add stubs for soc_css_init functions

Add TC specific stubs for both soc_css_init_nic400 and
soc_css_init_pcie. We do not require any initialisation of these
components for TC platforms.

Ch

fix(tc): add stubs for soc_css_init functions

Add TC specific stubs for both soc_css_init_nic400 and
soc_css_init_pcie. We do not require any initialisation of these
components for TC platforms.

Change-Id: If0129acd1050a56878cb9c3041a033192c88da57
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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Merge "fix(qemu): allocate space for GPT bitlock" into integration

feat(s32g274a): enable BL2 early clocks

s32cc_init_early_clks will be used to increase the frequency of the
clocks which have a performance impact on BL2 boot. This set includes
A53, XBAR, DDR and L

feat(s32g274a): enable BL2 early clocks

s32cc_init_early_clks will be used to increase the frequency of the
clocks which have a performance impact on BL2 boot. This set includes
A53, XBAR, DDR and Linflex clocks. For now, it will only contain the
frequency set for FXOSC. More clock management will be added in the next
commits.

Change-Id: Ie85465884de02f5082185f91749f190f40249c2e
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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Merge "refactor(st): change method to get GIC base addresses" into integration

Merge "feat(mediatek): configure DEV_IRQ as G1S interrupt" into integration

Merge "feat(ast2700): set up CPU clock frequency by SCU" into integration

feat(ast2700): set up CPU clock frequency by SCU

Modify generic timer frequency by SCU setting
1. check SCU_CPU_HW_STRAP1 using HPLL or MPLL
SCU_CPU_HW_STRAP1[4]=1, using HPLL
SCU_CPU_HW_STRAP1[

feat(ast2700): set up CPU clock frequency by SCU

Modify generic timer frequency by SCU setting
1. check SCU_CPU_HW_STRAP1 using HPLL or MPLL
SCU_CPU_HW_STRAP1[4]=1, using HPLL
SCU_CPU_HW_STRAP1[4]=0, using MPLL

2. read HPLL or MPLL
HPLL: frequency setting in SCU_CPU_HW_STRAP1[2:3]
MPLL: CLKIN_25M with mul and div setting from SCU_CPU_MPLL

Change-Id: I31eb10107b9da7c6746887ba36ead8ca61d86aae
Signed-off-by: Kevin Chen <kevin_chen@aspeedtech.com>

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Merge "feat(zynqmp): enable ENABLE_LTO flag" into integration

feat(s32g274a): use s32cc clock driver

To enable early clocks, such as A53, XBAR, and others, the clock driver
compilation should be included as part of the BL2 stage.

Change-Id: I17ba195d8c3cf3f91

feat(s32g274a): use s32cc clock driver

To enable early clocks, such as A53, XBAR, and others, the clock driver
compilation should be included as part of the BL2 stage.

Change-Id: I17ba195d8c3cf3f91bd333a00d4a4af2f1f472b7
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(st-reset): add stm32mp2_reset driver

This driver manages the resets of the peripherals embedded in STM32MP2.
Like clock driver, it also uses the RCC peripheral.

Change-Id: I8217891bdf1b847925a

feat(st-reset): add stm32mp2_reset driver

This driver manages the resets of the peripherals embedded in STM32MP2.
Like clock driver, it also uses the RCC peripheral.

Change-Id: I8217891bdf1b847925aad77f3f6ef542f08d1fba
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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feat(st-clock): add STM32MP2 clock driver

This driver manages the clocks on STM32MP2 platforms.
It uses a dedicated RCC (Reset and Clock Control) peripheral.

Change-Id: I6ba2173e73222269a2dfca4c689

feat(st-clock): add STM32MP2 clock driver

This driver manages the clocks on STM32MP2 platforms.
It uses a dedicated RCC (Reset and Clock Control) peripheral.

Change-Id: I6ba2173e73222269a2dfca4c6897229276a150c0
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>

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feat(st-reset): add system reset management

Add the system reset management into the stm32mp
reset driver.

Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: I748f10de2398e1323160f479

feat(st-reset): add system reset management

Add the system reset management into the stm32mp
reset driver.

Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: I748f10de2398e1323160f479f99e92abd2f65dca

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fix(arm): string split into two lines causing error

Fix the code related error message when user provides RESET_TO_BL31=1 to
the make command but fails to provide "ARM_PRELOADED_DTB_BASE" macro at
t

fix(arm): string split into two lines causing error

Fix the code related error message when user provides RESET_TO_BL31=1 to
the make command but fails to provide "ARM_PRELOADED_DTB_BASE" macro at
the same command line. Remove the line break from the error string
causing the code error.

Additionally, make doesn't parse quote marks in strings, thus remove
quote marks within error strings in this file.

Change-Id: Ic131b6febebfb420ed588fe4fb0853cbdae0afb8
Signed-off-by: Salman Nabi <salman.nabi@arm.com>

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feat(zynqmp): enable ENABLE_LTO flag

Enabling Link Time Optimization in platform.mk for AMD-Xilinx
ZynqMP platform optimizes TF-A size.
With ENABLE_LTO=0, the release bl31.elf size is 86098.
With EN

feat(zynqmp): enable ENABLE_LTO flag

Enabling Link Time Optimization in platform.mk for AMD-Xilinx
ZynqMP platform optimizes TF-A size.
With ENABLE_LTO=0, the release bl31.elf size is 86098.
With ENABLE_LTO=1, the release bl31.elf size reduces to 81866.
The size difference in OCM is 4232 bytes, saving up to 4KB.

Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: I6d5001a9ac250e3a87b958e9b665962a917265d6

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refactor(qemu-sbsa): use fdt_read_uint32_default more

We have fdt_read_uint32_default() function which allows us to use less
temporary variables. Let make use of it where applicable.

Signed-off-by:

refactor(qemu-sbsa): use fdt_read_uint32_default more

We have fdt_read_uint32_default() function which allows us to use less
temporary variables. Let make use of it where applicable.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I6fc8a87d5aac427703fd3c8b689e153ed58fa8b7

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Merge "feat(qemu-sbsa): handle the information of CPU topology" into integration

feat(qemu-sbsa): handle the information of CPU topology

We add the support for adding cpus/topology to device tree in sbsaQemu
platform, and we can get this information via SMC calls:

- counting th

feat(qemu-sbsa): handle the information of CPU topology

We add the support for adding cpus/topology to device tree in sbsaQemu
platform, and we can get this information via SMC calls:

- counting the number of sockets
- counting the number of clusters in one socket
- counting the number of cores in one cluster
- counting the number of threads in one core

Signed-off-by: Xiong Yining <xiongyining1480@phytium.com.cn>
Change-Id: I0059a5c7bb7055aba1aa5ec5bfd0ec78801874f8

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Merge changes from topic "fpga_update" into integration

* changes:
feat(fpga): enable new CPU features
feat(cpufeat): upgrade PMU to v8 (FEATURE_DETECTION)

Merge "fix(versal): remove check for bl32 load address" into integration

fix(versal): remove check for bl32 load address

With PLM firmware version 2024.1 the bl32 load address is set
correctly in handoff parameters.
Hence the check to initialize bl32 load address when bl

fix(versal): remove check for bl32 load address

With PLM firmware version 2024.1 the bl32 load address is set
correctly in handoff parameters.
Hence the check to initialize bl32 load address when bl32
load address is indicated as 0 in handoff is removed.

Change-Id: I322b8d2fc1137297142704ea1087c185e16177cc
Signed-off-by: Amit Nagal <amit.nagal@amd.com>

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fix(versal-net): remove check for bl32 load address

With PLM firmware version 2024.1 the bl32 load address is set
correctly in handoff parameters.
Hence the check to initialize bl32 load address whe

fix(versal-net): remove check for bl32 load address

With PLM firmware version 2024.1 the bl32 load address is set
correctly in handoff parameters.
Hence the check to initialize bl32 load address when bl32
load address is indicated as 0 in handoff is removed.

Change-Id: Ie927787129816e79d43ba4803f6916e20d81458a
Signed-off-by: Amit Nagal <amit.nagal@amd.com>

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refactor(st): change suffix for SYSCFG functions

This patch replaces the suffix "stm32mp1_" in the SYSCFG drivers
with "stm32mp_". By using a common suffix for function names, we can
avoid issues or

refactor(st): change suffix for SYSCFG functions

This patch replaces the suffix "stm32mp1_" in the SYSCFG drivers
with "stm32mp_". By using a common suffix for function names, we can
avoid issues or platform compilation flags when a driver
needs to access SYSCFG across different platforms.

Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: I24407852c085abd843ef4cdef235c022a5e57a85

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