refactor(dice): save parent context handle

Improve the restart handling of DPE. In the case of a restart
scenario where only that core is restarted which executes
the DPE client, but the core execut

refactor(dice): save parent context handle

Improve the restart handling of DPE. In the case of a restart
scenario where only that core is restarted which executes
the DPE client, but the core executes the DPE service
remains up and running. In this case, client needs to save
a valid context handle to be able to send commands again
to the DPE service during the new boot sequence.

BL1 saves a valid parent context handle to SDS
before passing the execution to BL2. This handle
can be used in case of a restart scenario when AP
is restarted but RSE is not. Because in that case
RSE does not save an initial context handle to SDS,
which meant to be used by AP during the boot process.

By then the very first initial context handle is
invalidated because it was already used in the
previous boot cycle by BL1.

BL2 does not need to do this, because the cold
boot starts with BL1.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: Id14eefd2ec758f89f672af176e4f5386a397fa35

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Merge changes from topic "nrd3_support" into integration

* changes:
feat(rdfremont): add support for measured boot at BL1 and BL2
feat(arm): mock support for CCA NV ctr
feat(rdfremont): fetch

Merge changes from topic "nrd3_support" into integration

* changes:
feat(rdfremont): add support for measured boot at BL1 and BL2
feat(arm): mock support for CCA NV ctr
feat(rdfremont): fetch attestation key and token from RSE
feat(psa): introduce generic library for CCA attestation
feat(rdfremont): initialize the rse comms driver
feat(rdfremont): helper to initialize rse-comms with AP-RSE MHUv3
fix(rse): include lib-psa to resolve build
feat(neoverse-rd): add MHUv3 channels on third gen multichip platforms
feat(neoverse-rd): add MHUv3 doorbell channels on third gen platforms
feat(rdfremont): initialize GPT on GPC SMMU block
feat(rdfremont): update Root registers page offset for SMMUv3
feat(rdfremont): enable MTE2 if present on the platform
feat(rdfremont): enable SVE for SWD and NS
feat(rdfremont): enable AMU if present on the platform
feat(rdfremont): enable MPAM if present on the platform
feat(rdfremont): add DRAM pas entries in pas table for multichip
feat(rdfremont): add implementation for GPT setup
feat(rdfremont): integrate DTS files for RD-Fremont variants
feat(rdfremont): add support for RD-Fremont-Cfg2
feat(rdfremont): add support for RD-Fremont-Cfg1
feat(rdfremont): add support for RD-Fremont
feat(neoverse-rd): add scope for RD-Fremont variants
feat(neoverse-rd): add multichip pas entries
feat(neoverse-rd): add pas definitions for third gen platforms
feat(neoverse-rd): add DRAM layout for third gen platforms
feat(neoverse-rd): add SRAM layout for third gen platforms
feat(neoverse-rd): add firmware definitions for third gen platforms
feat(neoverse-rd): add RoS definitions for third gen platforms
feat(neoverse-rd): add CSS definitions for third gen platforms

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refactor(st): rename plat_set_image_source

The function is only used in this file and is static, no need to have
plat_ prefix. And as it is used only in case of FWU, when looking in
metadata, add it

refactor(st): rename plat_set_image_source

The function is only used in this file and is static, no need to have
plat_ prefix. And as it is used only in case of FWU, when looking in
metadata, add it in the function name.

Suggested-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I925c9c517216cf93bd74308c280c0f22c7734490

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fix(tc): add SCP_BL2 to RSE measured boot

SCP_BL2 is part of CCA's TCB. The SCP_BL1 is loaded
by RSE. It has already added to the platform
attestation token. SCP_BL2 was missed, so it is
fixed now.

fix(tc): add SCP_BL2 to RSE measured boot

SCP_BL2 is part of CCA's TCB. The SCP_BL1 is loaded
by RSE. It has already added to the platform
attestation token. SCP_BL2 was missed, so it is
fixed now.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: Ic87743564136f03a901c90ff1ec614f5965b9a47

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Merge "fix(plat/marvell/a3k): reset GIC before resetting via CM3 secure coprocessor" into integration

Merge "refactor(qemu): use the example CCA platform token from iat-verifier" into integration

feat(st): add FWU with boot from NAND

Add the NAND use case in FWU boot. Like the NOR, NAND FWU won't use
a real partition UUID to find the correct FIP, but the UUID from
metadata will correspond wi

feat(st): add FWU with boot from NAND

Add the NAND use case in FWU boot. Like the NOR, NAND FWU won't use
a real partition UUID to find the correct FIP, but the UUID from
metadata will correspond with a hardcoded offset in the NAND.
Implement the plat_try_next_boot_source to load
backup partition on specific device.

Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@foss.st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I1dc544c479743d0ca2aace6e8214813d75637f50

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feat(st): manage backup partitions for NAND devices

Register a try_nand_backup_partitions() handler to plat_try_images_ops
to manage backup partition when booting from NAND devices.

Signed-off-by:

feat(st): manage backup partitions for NAND devices

Register a try_nand_backup_partitions() handler to plat_try_images_ops
to manage backup partition when booting from NAND devices.

Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@foss.st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ibee082b7b059b9e2ed502b7bbcda7464e5d9e251

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feat(bl): add plat handler for image loading

In case of load error, platform may need to try another instance, either
from another storage, or from the same storage in case of PSA FWU. On
MTD device

feat(bl): add plat handler for image loading

In case of load error, platform may need to try another instance, either
from another storage, or from the same storage in case of PSA FWU. On
MTD devices such as NAND, it is required to define backup partitions.
A new function plat_setup_try_img_ops() should be called by platform
code to register handlers (plat_try_images_ops) to manage loading
other images.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Change-Id: Ideaecaf296c0037a26fb4e6680f33e507111378a

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refactor(bl)!: remove unused plat_try_next_boot_source

The plat_try_next_boot_source() API is not used by any upstream platform
and not used by platforms that asked for this API. It is then removed.

refactor(bl)!: remove unused plat_try_next_boot_source

The plat_try_next_boot_source() API is not used by any upstream platform
and not used by platforms that asked for this API. It is then removed.
It will be replaced with a more generic interface in next patch.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I298c7acace8c5efb3c66422d8d9280ecd08e5ade

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Merge changes from topic "dualroot_dtb" into integration

* changes:
refactor(fvp): add CoT desc dtsi
feat(arm): add COT_DESC_IN_DTB option for Dualroot
feat(fvp): add Dualroot CoT in DTB suppo

Merge changes from topic "dualroot_dtb" into integration

* changes:
refactor(fvp): add CoT desc dtsi
feat(arm): add COT_DESC_IN_DTB option for Dualroot
feat(fvp): add Dualroot CoT in DTB support
feat(dt-bindings): introduce Dualroot CoT DTB

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feat(stm32mp1): always boot at 650MHz

Switching to higher CPU frequencies requires a dedicated chip version
(STM32MP1xxD or STM32MP1xxF), and increase CPU voltage. To avoid
re-configuring I2C and PM

feat(stm32mp1): always boot at 650MHz

Switching to higher CPU frequencies requires a dedicated chip version
(STM32MP1xxD or STM32MP1xxF), and increase CPU voltage. To avoid
re-configuring I2C and PMIC before and after applying clock tree,
always boot at 650MHz, which is the frequency for nominal voltage.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Id05a3ee17e7dd57e2d64dc06f8f1e7f9cb21e110

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Merge "fix(allwinner): remove unneeded header inclusion" into integration

Merge changes from topic "mb/refactor-cot" into integration

* changes:
refactor(juno): add explicit entry for HW_CONFIG in BL2 CoT file
refactor(auth): remove HW_CONFIG reference from BL1 CoT fi

Merge changes from topic "mb/refactor-cot" into integration

* changes:
refactor(juno): add explicit entry for HW_CONFIG in BL2 CoT file
refactor(auth): remove HW_CONFIG reference from BL1 CoT file

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fix(allwinner): remove unneeded header inclusion

Nothing in sunxi_bl31_setup.c uses any functionality provided by the
fdt_wrappers file, so remove its inclusion from the header list.

Change-Id: I47

fix(allwinner): remove unneeded header inclusion

Nothing in sunxi_bl31_setup.c uses any functionality provided by the
fdt_wrappers file, so remove its inclusion from the header list.

Change-Id: I47031a58add2f85e757e75d8578f4e8e21ef65ea
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge "fix(imx): disable DRAM retention by default on i.MX8MQ" into integration

Merge changes from topic "xlnx_fix_cpu_pwrdwn_handling" into integration

* changes:
fix(xilinx): handle power down event if SGI not registered
fix(xilinx): register for idle callback

feat(versal2): add support for AMD Versal Gen 2 platform

New SoC is a78 based with gicv3 and uart over pl011. Communication
interfaces are similar to Versal NET platform. System starts with AMD PLM

feat(versal2): add support for AMD Versal Gen 2 platform

New SoC is a78 based with gicv3 and uart over pl011. Communication
interfaces are similar to Versal NET platform. System starts with AMD PLM
firmware which loads TF-A(bl31) to memory, which is already configured, and
jumps to it. PLM also prepare handoff structure for TF-A with information
what components were load and flags which indicate which EL level SW should
be started.

Change-Id: I5065b1b7ec4ee58e77dc4096747758480c84009c
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>

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feat(rdfremont): add support for measured boot at BL1 and BL2

RD-Fremont platforms include Runtime Security Engine (RSE) as the
hardware crypto module. Add rse_measured_boot driver based platform
ho

feat(rdfremont): add support for measured boot at BL1 and BL2

RD-Fremont platforms include Runtime Security Engine (RSE) as the
hardware crypto module. Add rse_measured_boot driver based platform
hooks to measure and record firmware image measurements.

Additionally, add support for measured boot at BL1 and BL2 boot stages
on RD-Fremont platforms. The patch adds the RSE measured boot metadata
that includes firmware image IDs, measurement slot number and other
information. It also initializes the AP communication with RSE over
AP-RSE root MHUv3 channel to pass firmware image measurements to RSE to
support extended measurements.

Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Change-Id: Ia1b0bf673e865b31862cb8af79c4c71a5ba4dbea

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feat(arm): mock support for CCA NV ctr

Arm reference design FVP platforms such as RD-Fremont do not implement
the CCA_FW_NVCOUNTER. Update firmware such that the implementation will
return TRUSTED_F

feat(arm): mock support for CCA NV ctr

Arm reference design FVP platforms such as RD-Fremont do not implement
the CCA_FW_NVCOUNTER. Update firmware such that the implementation will
return TRUSTED_FW_NVCOUNTER when the caller requests the CCA NV counter.
This allows the platforms to use the CCA CoT on FVP platforms.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Change-Id: Ifab724fae63857056b3eeb44eeefc15c4c610eed

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feat(rdfremont): fetch attestation key and token from RSE

Use the delegated attestation driver to fetch platform attestation token
and Realm attestation key from RSE over the AP-RSE comms interface.

feat(rdfremont): fetch attestation key and token from RSE

Use the delegated attestation driver to fetch platform attestation token
and Realm attestation key from RSE over the AP-RSE comms interface.

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Change-Id: Id0cfd82ef79598cd8368ba017c145bf34d502e65

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feat(rdfremont): initialize the rse comms driver

Define platform specific API to fetch base address for secure or root
MHUv3 between AP-RSE invoke rse-comms driver initialization bl31
platform setup

feat(rdfremont): initialize the rse comms driver

Define platform specific API to fetch base address for secure or root
MHUv3 between AP-RSE invoke rse-comms driver initialization bl31
platform setup stage.

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Change-Id: Id79bcdb2fda6cdf394f4e02f67d1c1a44d5ddf23

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feat(rdfremont): helper to initialize rse-comms with AP-RSE MHUv3

Add a helper function to initialize rse_comms on RD-Fremont platforms
with AP-RSE MHUv3 postbox and mailbox register frames.

Signed

feat(rdfremont): helper to initialize rse-comms with AP-RSE MHUv3

Add a helper function to initialize rse_comms on RD-Fremont platforms
with AP-RSE MHUv3 postbox and mailbox register frames.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Change-Id: Ic390517a8810df195a2582793b81afdbff5ffa15

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feat(neoverse-rd): add MHUv3 channels on third gen multichip platforms

Add MHUv3 doorbell channel information to scmi_channel_plat_info_t for
third generation of multichip Neoverse reference design

feat(neoverse-rd): add MHUv3 channels on third gen multichip platforms

Add MHUv3 doorbell channel information to scmi_channel_plat_info_t for
third generation of multichip Neoverse reference design platforms.

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Change-Id: Ie4ebf47a10f2f6e33c7ecfc8008e30bacc62bf3d

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feat(neoverse-rd): add MHUv3 doorbell channels on third gen platforms

Define and use a new scmi_channel_plat_info_t structure specific to
third generation Neoverse platforms in order to use MHUv3 do

feat(neoverse-rd): add MHUv3 doorbell channels on third gen platforms

Define and use a new scmi_channel_plat_info_t structure specific to
third generation Neoverse platforms in order to use MHUv3 doorbell
channels. The structure uses the existing mhu_ring_doorbell method for
ring_doorbell implementation.

Signed-off-by: Shriram K <shriram.k@arm.com>
Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Change-Id: Icf3be5305df94ba944038a4d4fdf0ccf32168650

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