Merge "refactor(st): change suffix for SYSCFG functions" into integration

fix(stm32mp1): skip OP-TEE header check if image base is NULL

In bl2_plat_handle_post_image_load(), if the image_base of OP-TEE
header image is 0, do not call optee_header_is_valid(). This can be
th

fix(stm32mp1): skip OP-TEE header check if image base is NULL

In bl2_plat_handle_post_image_load(), if the image_base of OP-TEE
header image is 0, do not call optee_header_is_valid(). This can be
the case when OP-TEE is not present in the FIP.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ic2d014e59665c9efa33bbce1bf2eb3b66cd6fb26

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Merge "fix(intel): add in watchdog for QSPI driver" into integration

Merge "fix(qemu): remove validate_ns_entrypoint" into integration

feat(allwinner): adjust H616 L2 cache size in DTB

The Allwinner H616 and its siblings come in different die revisions,
some have 256 KB of L2 cache, some have 1 MB. This prevents a single
static cac

feat(allwinner): adjust H616 L2 cache size in DTB

The Allwinner H616 and its siblings come in different die revisions,
some have 256 KB of L2 cache, some have 1 MB. This prevents a single
static cache description in the devicetree.

Use the cache size ID register (CCSIDR_EL1) to query the topology of the
L2 cache, and adjust the cache-sets and cache-size properties in the L2
cache DT node accordingly.

The ARM ARM does not promise (anymore) that the cache size can be derived
*architecturally* from this register, but the reading is definitely
correct for the Arm Cortex-A53 core used.

Change-Id: Id7dc324d783b8319fe5df6164be2f941d4cac82d
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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feat(allwinner): h616: add support for AXP717 PMIC

On at least one new device we see an Allwinner H700 SoC paired with the
X-Powers AXP717 PMIC. In contrast to the small AXP313, this is a quite
comp

feat(allwinner): h616: add support for AXP717 PMIC

On at least one new device we see an Allwinner H700 SoC paired with the
X-Powers AXP717 PMIC. In contrast to the small AXP313, this is a quite
complete PMIC, with many voltage rails, battery and USB-C charging
support. It supports both RSB and I2C control options.

Add the compatible string to the list of checked devices. The AXP717
apparently does not feature a version ID register, but we read 0xff from
that address 0x3, so use this as an indication of its presence, since
this value differs from what we read from the other PMICs.
The register offset and bit position for the power off functionality is
again different, but easy to put into our switch/case.

Setting up regulators in TF-A is now somewhat obsolete, since U-Boot
does a much better job in this now, and can figure out which regulators
are actually needed. So we don't add the regulator setup code, and just
use the PMIC for the power-off functionality.

Change-Id: Ie6b4c91517014adcc79d9a3459c75545fa3a63e6
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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feat(allwinner): h616: add support for AXP313 PMIC

Many newer boards with the H616 and its sibling H618 are now paired
with the X-Powers AXP313 PMIC. This is a simpler PMIC, with only a few
voltage

feat(allwinner): h616: add support for AXP313 PMIC

Many newer boards with the H616 and its sibling H618 are now paired
with the X-Powers AXP313 PMIC. This is a simpler PMIC, with only a few
voltage rails and no extra functionality except the power key support.
In contrast to the AXP305 it can only be controlled via I2C.

Add a check to look for the AXP313 compatible string in the devicetree,
and set the PMIC type and I2C address accordingly, if one is found.
With only very few voltage rails available, all of them are mostly in
use and are thus enabled at reset already, so we can skip the regulator
setup entirely.

Change-Id: I01962854109e43793b4f56553c1ca9e1f752e30d
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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feat(allwinner): h616: add I2C PMIC support

The X-Powers AXP305 PMIC can be controlled via both I2C or RSB (an
Allwinner specific bus similar to I2C), but we chose to use only RSB,
because that's ea

feat(allwinner): h616: add I2C PMIC support

The X-Powers AXP305 PMIC can be controlled via both I2C or RSB (an
Allwinner specific bus similar to I2C), but we chose to use only RSB,
because that's easier to program and also used by Linux. The AXP313a
PMIC however supports only I2C, so we need to support both buses, and
need to decide which to use at runtime.

Prepare the PMIC code to add (back) I2C support. We initially used I2C
on the H6/AXP805 combination, but replaced that later with RSB. So this
patch is bringing some of that older code back.

The decision whether to use I2C or RSB is made by the devicetree, since
on some boards even RSB capable PMICs are controlled via I2C, since they
share the bus with only I2C capable devices, for instance RTCs.

At the moment this will still use RSB to drive the AXP305, but the
(dynamic) I2C code will be used shortly to support the AXP313.

This increases the code size by one 4K page, but with 80K out of the
reserved 256K we are still very far away from our limit.

Change-Id: I65c1e7df93dbd2dcd171b3fc486533a2948cc75b
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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refactor(allwinner): h616: prepare for more than one PMIC model

Most devices based on Allwinner SoCs come with a certain fixed
combination of Power Management ICs (PMICs) and SoC, for instance the
A

refactor(allwinner): h616: prepare for more than one PMIC model

Most devices based on Allwinner SoCs come with a certain fixed
combination of Power Management ICs (PMICs) and SoC, for instance the
A64 with the AXP803, or the H6 with the AXP805. This allowed us to
include the respective PMIC support code into each build target at build
time.

Similarly on H616 devices we initially saw only the AXP305, but for a
while now the simpler (and cheaper) AXP313a is a popular companion to
the H616 on many new boards. On at least one new device the AXP717 is
used as well.
With some rudimentary AXP version check in place we at least detected
the case of an unsupported SoC, but threw an error message, and lost
support for powering off the device.

Refactor the existing PMIC code to be able to support more than one
PMIC model, detected at runtime. For this we use a variable for the RSB
runtime address instead of hardcoding the address used on the AXP305,
and read the hardware bus address from the devicetree.
Also we look up the used PMIC in the devicetree, and set the PMIC model
accordingly. To be on the safe side, we also confirm the real PMIC used
by checking its version register and comparing that with the expected
value. Finally the register offset and value to power off the PMIC is
moved direclty into the platform code, as those values differ between
the different PMICs.

This is just refactoring and better error report, we still only support
the AXP305 on RSB at the moment.

Change-Id: I00b26ce4d30bb570ee1cd4979d0cdc9d6c020729
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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feat(mt8192): update memory protect region

SCP memory protect region need to align to SCP DRAM range.
Refer to
https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/bas

feat(mt8192): update memory protect region

SCP memory protect region need to align to SCP DRAM range.
Refer to
https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/baseboard/mtscp-rv32i/baseboard.h;l=132

Change-Id: I7d9444d5339f71e6bfdd9999a217e0c177e8199f
Signed-off-by: Kiwi Liu <kiwi.liu@mediatek.corp-partner.google.com>

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feat(mt8195): update memory protect region

SCP memory protect region need to align to SCP DRAM range.
Refer to
https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/bas

feat(mt8195): update memory protect region

SCP memory protect region need to align to SCP DRAM range.
Refer to
https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/baseboard/mtscp-rv32i/baseboard.h;l=149

Change-Id: I7b104c8ea8ee7f13d829a79f0a310d93ea466215
Signed-off-by: Kiwi Liu <kiwi.liu@mediatek.corp-partner.google.com>

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Merge "feat(rpi5): add PCI SMCCC support" into integration

fix(tc): enable MTE2 unconditionally

Keeping the MTE2 enablement under the SPMD check is breaking for FPGA
and CI test, as SPMD is absent in these cases.

Enable MTE2 unconditionally so that all the

fix(tc): enable MTE2 unconditionally

Keeping the MTE2 enablement under the SPMD check is breaking for FPGA
and CI test, as SPMD is absent in these cases.

Enable MTE2 unconditionally so that all the supported platforms can use
it.

Change-Id: Id86893f0e2767a8686c3dca0ea092907d5c107ba
Signed-off-by: Tintu Thomas <tintu.thomas@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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feat(rcar3): populate kaslr-seed in next stage DT

The SCEG CC6.3S which contains TRNG is only accessible from secure
world. Pull 8 random bytes out of the TRNG and pass them to the next
stage via DT

feat(rcar3): populate kaslr-seed in next stage DT

The SCEG CC6.3S which contains TRNG is only accessible from secure
world. Pull 8 random bytes out of the TRNG and pass them to the next
stage via DT fragment as /chosen/kaslr-seed property, so Linux can
use those random bytes to initialize KASLR in case it is compiled
with CONFIG_RANDOMIZE_BASE .

Linux before this patch prints early on boot:
KASLR disabled due to lack of seed

Linux after this patch prints early on boot:
KASLR enabled

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: Ie05473e4e15d348febaca208247541e8a1532534

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Merge changes from topic "add_s32cc_fxosc_clk" into integration

* changes:
feat(s32g274a): enable BL2 early clocks
feat(nxp-clk): implement set_rate for oscillators
feat(nxp-clk): add oscillat

Merge changes from topic "add_s32cc_fxosc_clk" into integration

* changes:
feat(s32g274a): enable BL2 early clocks
feat(nxp-clk): implement set_rate for oscillators
feat(nxp-clk): add oscillator clock objects
feat(nxp-clk): add minimal set of S32CC clock ids

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fix(tc): don't enable TZC on TC3

TZC is being replaced by MSF module on TC3. For fixing boot failure on
TC3, don't enable TZC module on the TC3 platform.

Change-Id: I4434cb28bf523be8dd882f5f8799223

fix(tc): don't enable TZC on TC3

TZC is being replaced by MSF module on TC3. For fixing boot failure on
TC3, don't enable TZC module on the TC3 platform.

Change-Id: I4434cb28bf523be8dd882f5f8799223642822ee2
Signed-off-by: Tintu Thomas <tintu.thomas@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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feat(zynqmp): move zynqmp platform to xlat tables v2

Switch to xlat table v2 version to add support for dynamic mapping
which is not supported in xlat table v1. It can be used for run
time DT mappin

feat(zynqmp): move zynqmp platform to xlat tables v2

Switch to xlat table v2 version to add support for dynamic mapping
which is not supported in xlat table v1. It can be used for run
time DT mapping. Also xlat table v1 version is going to be
deprecated that's why switch is necessary and removed unused xlat
table v1 macro from platform.mk.
With ENABLE_LTO enabled, size difference in OCM between xlat
table v2 and xlat table v1 release is 82193 - 82058 = 135 bytes.

Change-Id: Ifec2e75fb19670e83dc761fc40a8c4cd5ed9087b
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Signed-off-by: Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>

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feat(tc): provide target_locality info of AP FW components

The target_locality attribute is meant to specify that
a certain SW component is expected to run and thereby
send DPE commands from a given

feat(tc): provide target_locality info of AP FW components

The target_locality attribute is meant to specify that
a certain SW component is expected to run and thereby
send DPE commands from a given security domain. The DPE
service must be capable of determining the locality of
a client on his own. RSE determines the client's locality
based on the MHU channel used for communication.

If the expected locality (specified by the parent component)
is not matching with the determined locality by DPE
service then command fails.

The goal is to protect against spoofing when a
context_handle is stolen and used by a component
that should not have access.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I96d255de231611cfed10eef4335a47b91c2c94de

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refactor(tc): rename DPE header

The new name is more generic. The goal to add here
all platform dependent defines / data / config which
is DPE related.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>

refactor(tc): rename DPE header

The new name is more generic. The goal to add here
all platform dependent defines / data / config which
is DPE related.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I5b521932c45d8a9c43ea2344dde83c210801cfee

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Merge "refactor(tc): use the example CCA platform token from iat-verifier" into integration

Merge "feat(tc): add uart node in spmc manifest" into integration

fix(tc): add stubs for soc_css_init functions

Add TC specific stubs for both soc_css_init_nic400 and
soc_css_init_pcie. We do not require any initialisation of these
components for TC platforms.

Ch

fix(tc): add stubs for soc_css_init functions

Add TC specific stubs for both soc_css_init_nic400 and
soc_css_init_pcie. We do not require any initialisation of these
components for TC platforms.

Change-Id: If0129acd1050a56878cb9c3041a033192c88da57
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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Merge "fix(qemu): allocate space for GPT bitlock" into integration

feat(s32g274a): enable BL2 early clocks

s32cc_init_early_clks will be used to increase the frequency of the
clocks which have a performance impact on BL2 boot. This set includes
A53, XBAR, DDR and L

feat(s32g274a): enable BL2 early clocks

s32cc_init_early_clks will be used to increase the frequency of the
clocks which have a performance impact on BL2 boot. This set includes
A53, XBAR, DDR and Linflex clocks. For now, it will only contain the
frequency set for FXOSC. More clock management will be added in the next
commits.

Change-Id: Ie85465884de02f5082185f91749f190f40249c2e
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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Merge "refactor(st): change method to get GIC base addresses" into integration