build: make Poetry optional

The Yocto team has requested that we do not use Poetry from within the
Makefile, as Yocto does not have network access during the build
process.

We want to maintain the

build: make Poetry optional

The Yocto team has requested that we do not use Poetry from within the
Makefile, as Yocto does not have network access during the build
process.

We want to maintain the current behaviour, so this change makes our use
of Poetry contigent on it being available in the environment.

Additionally, explicitly passing an empty toolchain parameter now allows
a tool to be *disabled* (e.g. passing `POETRY=` will prevent the build
system from trying to use Poetry).

Change-Id: Ibf552a3fee1eaadee767a1b948b559700083b401
Signed-off-by: Chris Kay <chris.kay@arm.com>

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fix(xilinx): fix comment about MEM_BASE/SIZE

Comment is not showing correct macro name that's why fix it.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I8bc38534309285af8a27ee43782e

fix(xilinx): fix comment about MEM_BASE/SIZE

Comment is not showing correct macro name that's why fix it.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I8bc38534309285af8a27ee43782e03e9d0470267

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fix(intel): update CCU configuration for Agilex5 platform

Update CCU configuration for DSU, FPGA2SOC, GIC_M, SMMU, PSS NOC, DCE0,
DCE1,DMI0, DMI1, L4 peripheral firewall, L4 system firewall, LWSOC2F

fix(intel): update CCU configuration for Agilex5 platform

Update CCU configuration for DSU, FPGA2SOC, GIC_M, SMMU, PSS NOC, DCE0,
DCE1,DMI0, DMI1, L4 peripheral firewall, L4 system firewall, LWSOC2FPGA,
SOCFPGA and TCU.

Change-Id: Id416d58b0115098b99a8dfdccb28a7d6f6747f75
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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feat(s32g274a): enable workaround for ERR051700

ERR051700 erratum applies to all S32G274A chip revisions; therefore,
it is enabled for the S32G274ARDB2 board.

Change-Id: I1ec436e99bc9328e42e74aef9d

feat(s32g274a): enable workaround for ERR051700

ERR051700 erratum applies to all S32G274A chip revisions; therefore,
it is enabled for the S32G274ARDB2 board.

Change-Id: I1ec436e99bc9328e42e74aef9d93f18e0f82bd7a
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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fix(s32g274a): workaround for ERR051700 erratum

ERR051700 erratum is present on all S32CC-based SoCs and relates to
reset. Releasing multiple Software Resettable Domains (SRDs) from
reset simultaneo

fix(s32g274a): workaround for ERR051700 erratum

ERR051700 erratum is present on all S32CC-based SoCs and relates to
reset. Releasing multiple Software Resettable Domains (SRDs) from
reset simultaneously, may cause a false error in the fault control
unit.

The workaround is to clear the SRD resets sequentially instead of
simultaneously.

Change-Id: I883bc223bf6834907259e6964a5702d7186e4c7f
Signed-off-by: Alexandru-Catalin Ionita <alexandru-catalin.ionita@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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Merge changes from topic "dynamic-toolchain" into integration

* changes:
build: allow multiple toolchain defaults
build: determine toolchain tools dynamically

feat(neoverse-rd): allow RESET_TO_BL31 for third gen platforms

Allow building RESET_TO_BL31 for third generation neoverse-rd
platforms.

Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subra

feat(neoverse-rd): allow RESET_TO_BL31 for third gen platforms

Allow building RESET_TO_BL31 for third generation neoverse-rd
platforms.

Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Signed-off-by: Rakshit Goyal <rakshit.goyal@arm.com>
Change-Id: I30256969e5671043b3e58c76922985f7252429af

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feat(arm): setup GPT in BL31 in RESET_TO_BL31 boot flow

In the normal boot flow, BL2 sets up the Granule Protection Tables
(GPT). As BL2 is not a part of RESET_TO_BL31, BL31 needs to set up GPT
for

feat(arm): setup GPT in BL31 in RESET_TO_BL31 boot flow

In the normal boot flow, BL2 sets up the Granule Protection Tables
(GPT). As BL2 is not a part of RESET_TO_BL31, BL31 needs to set up GPT
for CPUs supporting FEAT_RME.

Signed-off-by: Rakshit Goyal <rakshit.goyal@arm.com>
Change-Id: I9ad16bd93ea9fbad422dd56e2ba1d600a30eea30

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feat(neoverse-rd): enable RESET_TO_BL31 for RD-V3

Update addresses for BL31, BL33 and NT_FW_CONFIG. Also add the PAS
entries to setup GPT tables in BL31.

Signed-off-by: Vivek Gautam <vivek.gautam@a

feat(neoverse-rd): enable RESET_TO_BL31 for RD-V3

Update addresses for BL31, BL33 and NT_FW_CONFIG. Also add the PAS
entries to setup GPT tables in BL31.

Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Signed-off-by: Rakshit Goyal <rakshit.goyal@arm.com>
Change-Id: I8947660bb96fdf2f178e560b387e4bc93bf68abf

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feat(neoverse-rd): add a routine to update NT_FW_CONFIG in BL31

In the BL1 based boot-flow, the non-secure DTB, NT_FW_CONFIG, is parsed
in BL2. As BL1 and BL2 are not part of RESET_TO_BL31, add supp

feat(neoverse-rd): add a routine to update NT_FW_CONFIG in BL31

In the BL1 based boot-flow, the non-secure DTB, NT_FW_CONFIG, is parsed
in BL2. As BL1 and BL2 are not part of RESET_TO_BL31, add support to
parse and configure this DTB in BL31. NT_FW_CONFIG contains the platform
information which is needed by BL33.

Signed-off-by: Rakshit Goyal <rakshit.goyal@arm.com>
Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Change-Id: Ib1fb5417c36523eb2ec02aa22845218de68809aa

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Merge changes I14df5d21,I7f952205,I6f52ec2c,Ibe0cacf8 into integration

* changes:
feat(stm32mp2-fdts): describe stpmic2 power supplies
feat(stm32mp2-fdts): add I2C7 pin muxing
feat(stm32mp2-fd

Merge changes I14df5d21,I7f952205,I6f52ec2c,Ibe0cacf8 into integration

* changes:
feat(stm32mp2-fdts): describe stpmic2 power supplies
feat(stm32mp2-fdts): add I2C7 pin muxing
feat(stm32mp2-fdts): add UART and I2C nodes for STM32MP2
feat(st-pmic): add STPMIC2 driver

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Merge "feat(stm32mp2): improve BL31 size management" into integration

Merge changes from topic "hm/tlc" into integration

* changes:
feat(handoff): make tl generation flexible
feat(tlc): add command gen-header
feat(tlc): add support for tox
refactor(tlc): fix s

Merge changes from topic "hm/tlc" into integration

* changes:
feat(handoff): make tl generation flexible
feat(tlc): add command gen-header
feat(tlc): add support for tox
refactor(tlc): fix static check errors and code style

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fix(intel): add cache invalidation during BL31 initialization

During warm boot, the data cache is invalidated before
enabling them in u-boot proper, this cache
invalidation (+ cleaning) leads to the

fix(intel): add cache invalidation during BL31 initialization

During warm boot, the data cache is invalidated before
enabling them in u-boot proper, this cache
invalidation (+ cleaning) leads to the sync-up of stale
values in the cache to be synced with the main memory.
So, before the cache cleaning is done in u-boot proper,
it is invalidated in BL31 so that the cache data gets in
sync with u-boot proper memory address space and when
u-boot proper does its initialization which in turn clears
its BSS and heap section.

Change-Id: Ic8d8672f1e371868be7f54f5a1fae9229ab15164
Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

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fix(intel): bridge ack timing issue causing fpga config hung

Increase the timeout of waiting for bridge ack to solve the
fpga config hung.

Change-Id: I967af02b336c296206b4947be718953ff8ca30cf
Signe

fix(intel): bridge ack timing issue causing fpga config hung

Increase the timeout of waiting for bridge ack to solve the
fpga config hung.

Change-Id: I967af02b336c296206b4947be718953ff8ca30cf
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

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Merge "feat(rk3588): enable crypto function" into integration

feat(stm32mp2): improve BL31 size management

Change the size of BL31 limit allocation to be half the sysram size.
Defining BL31_PROGBITS_LIMIT to detect overflows.

Signed-off-by: Maxime Méré <maxim

feat(stm32mp2): improve BL31 size management

Change the size of BL31 limit allocation to be half the sysram size.
Defining BL31_PROGBITS_LIMIT to detect overflows.

Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: Iccc1cc0826b8113a3c2fd6ffa77ca419795854d3

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Merge "fix(rpi3): manually populate CNTFRQ reg" into integration

fix(st): support device tree DDR sizes higher than 16Gbits for aarch64

In that case, memory address space is higher than 4GB, so 32-bits
addressing is not enough.
Get st,mem-size property value on 6

fix(st): support device tree DDR sizes higher than 16Gbits for aarch64

In that case, memory address space is higher than 4GB, so 32-bits
addressing is not enough.
Get st,mem-size property value on 64bits (size_t type in structures).

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: I1df23bfa7a850fc3f5a4ef9fc5d2f76ab6c6dea8

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feat(st-pmic): add STPMIC2 driver

The STPMIC2 embeds 15 regulators with various
properties, and is designed to supply the STM32MP2
SOC. This driver handles a minimal set of feature
to handle the boo

feat(st-pmic): add STPMIC2 driver

The STPMIC2 embeds 15 regulators with various
properties, and is designed to supply the STM32MP2
SOC. This driver handles a minimal set of feature
to handle the boot of a board.

Signed-off-by: Pascal Paillet <p.paillet@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: Ibe0cacf8aec2871eb9a86ec16cbbd18d3745fe9e

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feat(handoff): make tl generation flexible

Make the process of compiling a TL from DT source flexible. Provide a
top level recipe to make it easier for developers to build a transfer
list. Clean up

feat(handoff): make tl generation flexible

Make the process of compiling a TL from DT source flexible. Provide a
top level recipe to make it easier for developers to build a transfer
list. Clean up integration of TLC into the build system.

Change-Id: I4466e27a457dfd5bf709dc3a360a2b63bf6030ce
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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fix(rpi3): manually populate CNTFRQ reg

The rpi3 does not initialize the generic timer in BL1, which is now
required to use the delay timer in the dTPM driver. This change sets the
counter frequency

fix(rpi3): manually populate CNTFRQ reg

The rpi3 does not initialize the generic timer in BL1, which is now
required to use the delay timer in the dTPM driver. This change sets the
counter frequency register (CNTFRQ) with the rpi3's system counter
frequency value, as a prerequisite for timer initialization, and then
initializes the generic timer all during BL1 setup.

Change-Id: I4e2475b63ce4a97653202f94f506b5d3edc4c1a7
Signed-off-by: Abhi Singh <abhi.singh@arm.com>

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feat(rk3588): enable crypto function

The CPU crypto is not default on when power up, need to enable it by
software.

Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
Change-Id: Ifee2eab5

feat(rk3588): enable crypto function

The CPU crypto is not default on when power up, need to enable it by
software.

Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
Change-Id: Ifee2eab55d9c13cef5f15926fb80016845e2a66d

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Merge "fix(xilinx): map PMC_GPIO device node to interrupt for wakeup source" into integration

fix(allwinner): enable dtb modifications for CPU idle states to the rich OS

Commit e2b18771fc2a0528dda18dbdaac08dd8530df25a ("feat(allwinner):
provide CPU idle states to the rich OS") added function

fix(allwinner): enable dtb modifications for CPU idle states to the rich OS

Commit e2b18771fc2a0528dda18dbdaac08dd8530df25a ("feat(allwinner):
provide CPU idle states to the rich OS") added functionality to amend
dtb, when SCPI as the PSCI backend is available. But this
functionality is disabled by default even for platforms, that support
it, like A64. As a result rich OS don't get information about
available CPU idle states.

Due to size constraints of A64 platform DEBUG=1 can be built with
dtb amend functionality only with LTO enabled. So ENABLE_LTO is
enabled by default for this platform.

```
aarch64-linux-gnu-ld.bfd: address 0x500dd of build/sun50i_a64/debug/bl31/bl31.elf section `.data' is not within region `RAM'
aarch64-linux-gnu-ld.bfd: BL31 image has exceeded its limit.
aarch64-linux-gnu-ld.bfd: region `RAM' overflowed by 224 bytes
```

To build with ENABLE_LTO=0 and DEBUG=1 it's required SUNXI_AMEND_DTB=0
to explicitly disable dtb amend functionality.

sun50i_r329 SUNXI_AMEND_DTB=1 DEBUG=1 build fails with 'region `RAM'
overflowed by 120 bytes'. To avoid unnecessary RAM consumption on
other resource-constraints platforms (like sun50i_r329)
SUNXI_AMEND_DTB is enabled only on sun50i_a64. Otherwise
On other platforms sunxi_idle_states are empty.

Signed-off-by: Andrey Skvortsov <andrej.skvortzov@gmail.com>
Change-Id: I81fcf31b5bd2bd02a9f3361a6a519632f087445d

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