fix(corstone-1000): fix Makefile error reporting

When trying to build for the Corstone-1000 platform without specifying a
valid TARGET_PLATFORM value, the "make" call reports a Makefile error
instea

fix(corstone-1000): fix Makefile error reporting

When trying to build for the Corstone-1000 platform without specifying a
valid TARGET_PLATFORM value, the "make" call reports a Makefile error
instead of the expected error messages pointing to the variable
omission:
====================
platform.mk: *** recipe commences before first target. Stop.
====================
This is due to the make's infamous special handling of the tab
character.

Fix the error report by replacing the tab with spaces.

Change-Id: I38264b6731793e5d5b929c189bb963e55bd5ce2d
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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fix(intel): update memcpy to memcpy_s

memcpy does not check the dst_size which may
create vulnerable issue as it can overflow the buffer.
Using memcpy_s which check the dst_size will help to
reduce

fix(intel): update memcpy to memcpy_s

memcpy does not check the dst_size which may
create vulnerable issue as it can overflow the buffer.
Using memcpy_s which check the dst_size will help to
reduce the risk. Also, this memcpy is always 4 bytes
each time.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I413e6ae2ee9330501703c4cd63b7943c6f55b4c7

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fix(intel): add in missing ECC register

This patch is to add in missing ECC register (INITSTAT)

Change-Id: Iecf03dc9597ec2884901c132fb9cef7e90ab06a0
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.

fix(intel): add in missing ECC register

This patch is to add in missing ECC register (INITSTAT)

Change-Id: Iecf03dc9597ec2884901c132fb9cef7e90ab06a0
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

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Merge changes from topics "rockchip", "rockchip-rk3588" into integration

* changes:
feat(rk3588): support SCMI for clock/reset domain
feat(rk3588): support rk3588

Merge changes from topic "stm32mp2_bl2_updates" into integration

* changes:
feat(stm32mp2): load fw-config file
feat(stm32mp2): add fw-config compilation
feat(stm32mp2-fdts): add fw-config fil

Merge changes from topic "stm32mp2_bl2_updates" into integration

* changes:
feat(stm32mp2): load fw-config file
feat(stm32mp2): add fw-config compilation
feat(stm32mp2-fdts): add fw-config files for STM32MP257F-EV1
feat(stm32mp2-fdts): add fw-config file
feat(stm32mp2-fdts): add clock tree for STM32MP257F-EV1
feat(stm32mp2): enable DDR sub-system clock
feat(stm32mp2): add fixed regulators support
feat(stm32mp2): print board info
feat(stm32mp2): display CPU info
feat(stm32mp2): get chip ID
feat(stm32mp2): add BL2 boot first steps
feat(stm32mp2): add defines for the PWR peripheral
feat(stm32mp2-fdts): add SD-card and eMMC support on STM32MP257F-EV1
feat(stm32mp2-fdts): add sdmmc pins definition
feat(stm32mp2-fdts): add sdmmc nodes in SoC DT file
feat(stm32mp2-fdts): add io_policies
feat(stm32mp2-fdts): remove pins-are-numbered

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Merge changes I23bdbbe1,Ic22ab741 into integration

* changes:
feat(intel): enable VAB support for Intel products
feat(intel): add in SHA384 authentication

Merge changes from topic "nxp-drivers/add-linflex-clk" into integration

* changes:
feat(nxp-clk): enable UART clock
feat(nxp-clk): add PERIPH PLL enablement

Merge "fix(xilinx): fix OVERRUN coverity violation" into integration

Merge changes from topic "jc/refact_el1_ctx" into integration

* changes:
feat(cm): enhance the cpu_context memory report
refactor(cm): remove el1 context when SPMD_SPM_AT_SEL2=1

Merge "fix(intel): update sip smc config addr for agilex5" into integration

refactor(cm): remove el1 context when SPMD_SPM_AT_SEL2=1

* Currently, EL1 context is included in cpu_context_t by default
for all the build configurations.
As part of the cpu context structure,

refactor(cm): remove el1 context when SPMD_SPM_AT_SEL2=1

* Currently, EL1 context is included in cpu_context_t by default
for all the build configurations.
As part of the cpu context structure, we hold a copy of EL1, EL2
system registers, per world per PE. This context structure is
enormous and will continue to grow bigger with the addition of
new features incorporating new registers.

* Ideally, EL3 should save and restore the system registers at its next
lower exception level, which is EL2 in majority of the configurations.

* This patch aims at optimising the memory allocation in cases, when
the members from the context structure are unused. So el1 system
register context must be omitted when lower EL is always x-EL2.

* "CTX_INCLUDE_EL2_REGS" is the internal build flag which gets set,
when SPD=spmd and SPMD_SPM_AT_SEL2=1 or ENABLE_RME=1.
It indicates, the system registers at EL2 are context switched for
the respective build configuration. Here, there is no need to save
and restore EL1 system registers, while x-EL2 is enabled.

Henceforth, this patch addresses this issue, by taking out the EL1
context at all possible places, while EL2 (CTX_INCLUDE_EL2_REGS) is
enabled, there by saving memory.

Change-Id: Ifddc497d3c810e22a15b1c227a731bcc133c2f4a
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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chore(cm): reorganise sctlr_el1 and tcr_el1 ctx code

SCTLR_EL1 and TCR_EL1 regs are included either as part of errata
"ERRATA_SPECULATIVE_AT" or under el1_sysregs_t context structure.
The code to wr

chore(cm): reorganise sctlr_el1 and tcr_el1 ctx code

SCTLR_EL1 and TCR_EL1 regs are included either as part of errata
"ERRATA_SPECULATIVE_AT" or under el1_sysregs_t context structure.
The code to write and read into these context entries, looks
repetitive and is invoked at most places.
This section is refactored to bring them under a static procedure,
keeping the code neat and easier to maintain.

Change-Id: Ib0d8c51bee09e1600c5baaa7f9745083dca9fee1
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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Merge changes from topic "mp/simd_ctxt_mgmt" into integration

* changes:
feat(fvp): allow SIMD context to be put in TZC DRAM
docs(simd): introduce CTX_INCLUDE_SVE_REGS build flag
feat(fvp): ad

Merge changes from topic "mp/simd_ctxt_mgmt" into integration

* changes:
feat(fvp): allow SIMD context to be put in TZC DRAM
docs(simd): introduce CTX_INCLUDE_SVE_REGS build flag
feat(fvp): add Cactus partition manifest for EL3 SPMC
chore(simd): remove unused macros and utilities for FP
feat(el3-spmc): support simd context management upon world switch
feat(trusty): switch to simd_ctx_save/restore apis
feat(pncd): switch to simd_ctx_save/restore apis
feat(spm-mm): switch to simd_ctx_save/restore APIs
feat(simd): add rules to rationalize simd ctxt mgmt
feat(simd): introduce simd context helper APIs
feat(simd): add routines to save, restore sve state
feat(simd): add sve state to simd ctxt struct
feat(simd): add data struct for simd ctxt management

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feat(nxp-clk): enable UART clock

Before this change, the internal oscillator clocked the UART with a
frequency of 48MHz. With the necessary support added, the UART clock
rate is increased to 125MHz

feat(nxp-clk): enable UART clock

Before this change, the internal oscillator clocked the UART with a
frequency of 48MHz. With the necessary support added, the UART clock
rate is increased to 125MHz by changing the clock source from FIRC to
PERIPH PLL PHI3.

Change-Id: I3160dc6860ebf441c9bea8eaf9d8d12de48bd647
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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fix(xilinx): fix OVERRUN coverity violation

This change fixes below MISRA violation:
CID 441243: Memory - corruptions (OVERRUN)
Overrunning callee's array of size 7 by passing argument "7UL" in ca

fix(xilinx): fix OVERRUN coverity violation

This change fixes below MISRA violation:
CID 441243: Memory - corruptions (OVERRUN)
Overrunning callee's array of size 7 by passing argument "7UL" in call to
"pm_ipi_send_sync".

Change-Id: Ie7fd9ccad058e97eb4b36c4f0e77be8bfb3e6006
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>

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feat(nxp-drivers): add Linflex flush callback

Implement a flush callback for the Linflex UART driver to avoid cases
where the BL31 stage reinitializes the console while there is ongoing TX
initiated

feat(nxp-drivers): add Linflex flush callback

Implement a flush callback for the Linflex UART driver to avoid cases
where the BL31 stage reinitializes the console while there is ongoing TX
initiated by the BL2.

Change-Id: Ic49852f809198362de1f993474c7c45f1439dc98
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(fvp): allow SIMD context to be put in TZC DRAM

This patch demonstrates the capability of SEPARATE_SIMD_SECTION build
flag through which the memory intensive SIMD context data structures
are all

feat(fvp): allow SIMD context to be put in TZC DRAM

This patch demonstrates the capability of SEPARATE_SIMD_SECTION build
flag through which the memory intensive SIMD context data structures
are allocated in a separate section withtin the TZC DRAM space.

Change-Id: Idf3f232a7960a8f84f279d496c76953a6dad2009
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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feat(fvp): add Cactus partition manifest for EL3 SPMC

This patch adds the SP partition manifest to boot Cactus SP on
EL3 SPMC to be used with FVP platform.

Change-Id: I88b36f6ac21ebba7fa93aef75dad7

feat(fvp): add Cactus partition manifest for EL3 SPMC

This patch adds the SP partition manifest to boot Cactus SP on
EL3 SPMC to be used with FVP platform.

Change-Id: I88b36f6ac21ebba7fa93aef75dad74bb9ee5c944
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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feat(simd): add rules to rationalize simd ctxt mgmt

Illegal combinations of build flags associated with SIMD context
management are flagged by the build system.

Change-Id: I3192af3889e1e864c7875778

feat(simd): add rules to rationalize simd ctxt mgmt

Illegal combinations of build flags associated with SIMD context
management are flagged by the build system.

Change-Id: I3192af3889e1e864c7875778616e167ba6894195
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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Merge changes from topic "ar/asymmetricSupport" into integration

* changes:
feat(tc): enable trbe errata flags for Cortex-A520 and X4
feat(cm): asymmetric feature support for trbe
refactor(err

Merge changes from topic "ar/asymmetricSupport" into integration

* changes:
feat(tc): enable trbe errata flags for Cortex-A520 and X4
feat(cm): asymmetric feature support for trbe
refactor(errata-abi): move EXTRACT_PARTNUM to arch.h
feat(cpus): workaround for Cortex-A520(2938996) and Cortex-X4(2726228)
feat(tc): make SPE feature asymmetric
feat(cm): handle asymmetry for SPE feature
feat(cm): support for asymmetric feature among cores
feat(cpufeat): add new feature state for asymmetric features

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feat(tc): enable trbe errata flags for Cortex-A520 and X4

Enable following erratas as per the TARGET_PLATFORM of TC
- ERRATA_A520_2938996
- ERRATA_X4_2726228

Signed-off-by: Manish Pandey <manish.

feat(tc): enable trbe errata flags for Cortex-A520 and X4

Enable following erratas as per the TARGET_PLATFORM of TC
- ERRATA_A520_2938996
- ERRATA_X4_2726228

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ia552473740c34867dd9fd619faf378adcb784821

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feat(tc): make SPE feature asymmetric

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ibf0fecb2a97cb0f3508e01e0907e61e3c437ac00

Merge changes from topic "romlib-fixes" into integration

* changes:
fix(romlib): wrap indirectly included functions
fix(arm): remove duplicate jumptable entry

Merge "fix(rdv3): remove NEED_* from RD-V3 makefile" into integration

feat(mt8188): update SVP region ID protection flow

- Extend the SVP region number from 1 to 10
- Mapping one region each time

Change-Id: I2dd517127018c71174f3d52a2118463370caf569
Signed-off-by: Gav

feat(mt8188): update SVP region ID protection flow

- Extend the SVP region number from 1 to 10
- Mapping one region each time

Change-Id: I2dd517127018c71174f3d52a2118463370caf569
Signed-off-by: Gavin Liu <gavin.liu@mediatek.com>

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