Merge "fix(intel): update all the platforms hand-off data offset value" into integration

Merge "feat(cpus): add support for cortex-a720ae" into integration

Merge "fix(tc): retain NS timer frame ID for TC2 as 0" into integration

fix(intel): correct macro naming

Correct macro naming to meet define macro standard.

Change-Id: Id0a091d67ef879a0f4c048bd9c2169c603ff4ce9
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

Merge "fix(allwinner): enable dtb modifications for CPU idle states to the rich OS" into integration

feat(intel): pinmux and power manager config for Agilex5 platform

Read the hand-off data and configure the pinmux
select, IO control, IO delay and use FPGA switch.
Configure the power manager PSS SR

feat(intel): pinmux and power manager config for Agilex5 platform

Read the hand-off data and configure the pinmux
select, IO control, IO delay and use FPGA switch.
Configure the power manager PSS SRAM power gate.

Change-Id: I2241018cbf2828182e8af84ddb214ce57e9f242a
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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fix(intel): update all the platforms hand-off data offset value

Move the hand-off data offset value from the common
platform header file to each socfpga platform specific
header file.

Change-Id: Ic

fix(intel): update all the platforms hand-off data offset value

Move the hand-off data offset value from the common
platform header file to each socfpga platform specific
header file.

Change-Id: Icfe917f788814c329659c44e298cf05d6e3d0dd9
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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refactor(fvp): add support for cluster power-on

All new FVP's have incorporated the following PYSR bits

bit 31 is cluster ON status
bit 30 is core ON status
bit 29 is thread ON status

So add suppo

refactor(fvp): add support for cluster power-on

All new FVP's have incorporated the following PYSR bits

bit 31 is cluster ON status
bit 30 is core ON status
bit 29 is thread ON status

So add support to check cluster power ON which is supported from
affinity-level-2

But older cores with no DSU still uses affinity-level-1 for cluster
power-on status.

Ref: https://developer.arm.com/documentation/100964/1125/Base-Platform/Base---components

Change-Id: Id86811b14685d9ca900021301e5e8b7d52189963
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge "fix(intel): fix CCU for cache maintenance" into integration

Merge "fix(intel): flush L1/L2/L3/Sys cache before HPS cold reset" into integration

Merge "fix(intel): update preloaded_bl33_base for legacy product" into integration

Merge "feat(intel): direct boot from TF-A to Linux for Agilex" into integration

chore(fvp): use correct dts for dynamiq cores

The default dts doesn't describe the core topology correctly - it uses a
two level affinity, while new cores use 3 level with MPIDR_EL1.MT set.
As a res

chore(fvp): use correct dts for dynamiq cores

The default dts doesn't describe the core topology correctly - it uses a
two level affinity, while new cores use 3 level with MPIDR_EL1.MT set.
As a result Linux doesn't discover secondary cores correctly unless this
is specifically provided on the command line. CI already accounts for
this in tf_config/fvp-dynamiq-aarch64-only.

Change-Id: I137b213cfc48d98b8856c113d4ec0bf6474d3e2d
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(stm32mp2): set PLAT_MAX_PWR_LVL to one

Set maximum power level to 1 as power management isn't implemented yet.

Change-Id: I26cefbb5e199944d371bf06a76b2c41f73d38585
Signed-off-by: Maxime Méré <m

fix(stm32mp2): set PLAT_MAX_PWR_LVL to one

Set maximum power level to 1 as power management isn't implemented yet.

Change-Id: I26cefbb5e199944d371bf06a76b2c41f73d38585
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>

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feat(stm32mp2): boot BL33 at EL1 or EL2

STM32 MPUs use U-Boot as BL33. It can handle being booted at EL2.
Add a new STM32MP_BL33_EL1 config boolean. If defined BL33 will start
at EL1 and with INIT_U

feat(stm32mp2): boot BL33 at EL1 or EL2

STM32 MPUs use U-Boot as BL33. It can handle being booted at EL2.
Add a new STM32MP_BL33_EL1 config boolean. If defined BL33 will start
at EL1 and with INIT_UNUSED_NS_EL2 defined to Iiitialize the unused EL2
registers.

Change BL33 spsr parameter in bl2_mem_params_descs[] to use MODE_EL2
or MODE_EL1 depending on this flag. Default to MODE_EL1 as kernel
isn't able to boot at EL2 yet.

Change-Id: I6a8b35280d454d8140d7b28f0a5fc9b9a5093d6d
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Signed-off-by: Christian Bruel <christian.bruel@foss.st.com>

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feat(stm32mp2): disable unsupported features

SPE and SVE for non-secure world are not supported on Arm v8.0.
Disable the corresponding flags. This also saves a bit of memory.

Change-Id: I323fb74103

feat(stm32mp2): disable unsupported features

SPE and SVE for non-secure world are not supported on Arm v8.0.
Disable the corresponding flags. This also saves a bit of memory.

Change-Id: I323fb7410393ea9711759be4c47848316fb68860
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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feat(amd): populate handoff from TL

Handoff structures are populated by executable entry point
information tag based bl32/bl33 entries present in transfer list.

The upstream code is having problem

feat(amd): populate handoff from TL

Handoff structures are populated by executable entry point
information tag based bl32/bl33 entries present in transfer list.

The upstream code is having problem with the last TL entry
particularly when the tags for two entries are same.
While tlc tool dumps all entries correctly, transfer_list_dump() in
upstream code does not provide information about the last entry in TL.

Enabling TRANSFER_LIST also enables BL1_SOURCES and BL2_SOURCES in
transfer_list.mk thereby enabling bl1/bl2 builds.
bl1/bl2 builds are disabled by turning off NEED_BL1/NEED_BL2
build flags.

Change-Id: I55ddccc1ab266cc5a609423d304a5e5c282e17f6
Signed-off-by: Amit Nagal <amit.nagal@amd.com>

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Merge changes I8d62253e,I320a0585 into integration

* changes:
feat(stm32mp2): initialize gic and delay timer in bl31_plat_arch_setup
feat(stm32mp2): add BL31 device tree support

fix(intel): fix CCU for cache maintenance

Fix CCU settings for cache maintenance.

Change-Id: I9af35a6ab7aa9ee20e05ba82d0a042948ac29a93
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Signed-

fix(intel): fix CCU for cache maintenance

Fix CCU settings for cache maintenance.

Change-Id: I9af35a6ab7aa9ee20e05ba82d0a042948ac29a93
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

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fix(intel): update preloaded_bl33_base for legacy product

Update preloaded_bl33_base for legacy product for Yocto.

The Yocto Jenkins build was initially configured to build products
where the start

fix(intel): update preloaded_bl33_base for legacy product

Update preloaded_bl33_base for legacy product for Yocto.

The Yocto Jenkins build was initially configured to build products
where the starting of the DDR is from 0x0000 0000. And if there is
no NS_image_offset set, the Jenkins is not able to acquire the correct
address offset to boot up the system. However, in the direct OS boot,
there is no issue as the user shall always include the address offset
during the compilation phase. Otherwise, the code shall execute the
default address offset. Besides that, this also provides the
flexibility to user to customize their SoC design by not restricted
to the default address.

SDMMC block size. It was changed due to the need when boot to Linux.
Kernel.itb size is big thus we have to increase the available reading
block size. Otherwise for normal U-boot and Zephyr it shall not be
reading a big block size to avoid "garbage" data.

Change-Id: I1c2a22db28bf0ada734563e40efd4f5749951273
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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fix(intel): flush L1/L2/L3/Sys cache before HPS cold reset

This fix is to flush and invalidate the caches before cold reset.
Issue happen where Agilex5 hardware does not support the caches flush.
Th

fix(intel): flush L1/L2/L3/Sys cache before HPS cold reset

This fix is to flush and invalidate the caches before cold reset.
Issue happen where Agilex5 hardware does not support the caches flush.
Thus software workaround is needed.

Change-Id: Ibfeecbc611d238a069ca72f8b833f319e794cd38
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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feat(intel): direct boot from TF-A to Linux for Agilex

Enable and update code for TF-A direct boot Linux
for Agilex platform.

Change-Id: Id95986b7015a2a01f0aff80e1c7d8f8bb8fb4637
Signed-off-by: Sie

feat(intel): direct boot from TF-A to Linux for Agilex

Enable and update code for TF-A direct boot Linux
for Agilex platform.

Change-Id: Id95986b7015a2a01f0aff80e1c7d8f8bb8fb4637
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

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Merge "feat(cpus): add support for arcadia cpu" into integration

feat(cpus): add support for cortex-a720ae

Add the basic CPU library code to support Cortex-A720AE.
The overall library code is adapted based on Cortex-A720 code.

Signed-off-by: David Hu <david.hu2@

feat(cpus): add support for cortex-a720ae

Add the basic CPU library code to support Cortex-A720AE.
The overall library code is adapted based on Cortex-A720 code.

Signed-off-by: David Hu <david.hu2@arm.com>
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>
Change-Id: I3d64dc5a3098cc823e656a5ad3ea05cd71598dc6

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feat(stm32mp2): initialize gic and delay timer in bl31_plat_arch_setup

For minimal BL31 setup, GIC and tick must be initialized.

Change-Id: I8d62253e93b77cd8ce8091ccc9ea88208bdd6053
Signed-off-by:

feat(stm32mp2): initialize gic and delay timer in bl31_plat_arch_setup

For minimal BL31 setup, GIC and tick must be initialized.

Change-Id: I8d62253e93b77cd8ce8091ccc9ea88208bdd6053
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>

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