Merge "feat(stm32mp2): add FWU support" into integration

Merge changes I7854e1ae,I214e4b2b,I000573e5 into integration

* changes:
feat(stm32mp2): add a runtime service for STGEN configuration
feat(stm32mp2): add common SMC runtime services
feat(stm32

Merge changes I7854e1ae,I214e4b2b,I000573e5 into integration

* changes:
feat(stm32mp2): add a runtime service for STGEN configuration
feat(stm32mp2): add common SMC runtime services
feat(stm32mp1): rework SVC services

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fix(tc): eliminate unneeded MbedTLS dependency

The rse_platform_api.h file includes certain MbedTLS headers,
introducing an unnecessary dependency when building the TC
platform with RSE support unco

fix(tc): eliminate unneeded MbedTLS dependency

The rse_platform_api.h file includes certain MbedTLS headers,
introducing an unnecessary dependency when building the TC
platform with RSE support unconditionally.
However, these headers are not required, as the BL31
implementation only initializes RSE communication,
which does not rely on MbedTLS.

Change-Id: If45122aaf158be128f8978422fd870dbb0a0d090
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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feat(mediatek): add vcp driver support

It is excepted that kernel vcp can request the vcp hw do
some security setting via SMC call services.

Signed-off-by: Xiangzhi Tang <xiangzhi.tang@mediatek.cor

feat(mediatek): add vcp driver support

It is excepted that kernel vcp can request the vcp hw do
some security setting via SMC call services.

Signed-off-by: Xiangzhi Tang <xiangzhi.tang@mediatek.corp-partner.google.com>
Change-Id: Ib5c01c1d72b3483262dcd821878e6e53ba9c681c

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fix(rk3399): fix unquoted .incbin for clang

While GCC doesn't complain about anything for .incbin, clang does:
"""
<instantiation>:6:10: error: expected string in '.incbin' directive
.incbin /build

fix(rk3399): fix unquoted .incbin for clang

While GCC doesn't complain about anything for .incbin, clang does:
"""
<instantiation>:6:10: error: expected string in '.incbin' directive
.incbin /build/rk3399/release/m0/rk3399m0.bin
^
plat/rockchip/rk3399/drivers/pmu/pmu_fw.S:20:1: note: while in macro instantiation
INCBIN """/build/rk3399/release/m0/rk3399m0.bin""", "rk3399m0_bin", ".sram.incbin"
^
<instantiation>:6:10: error: expected string in '.incbin' directive
.incbin /build/rk3399/release/m0/rk3399m0pmu.bin
^
plat/rockchip/rk3399/drivers/pmu/pmu_fw.S:21:1: note: while in macro instantiation
INCBIN """/build/rk3399/release/m0/rk3399m0pmu.bin""", "rk3399m0pmu_bin", ".pmusram.incbin"
^
"""

Adding quotes around \file in .incbin fixes the clang issue but GCC now
complains:
"""
plat/rockchip/rk3399/drivers/pmu/pmu_fw.S: Assembler messages:
plat/rockchip/rk3399/drivers/pmu/pmu_fw.S:14: Error: junk at end of line, first unrecognized character is `/'
plat/rockchip/rk3399/drivers/pmu/pmu_fw.S:20: Info: macro invoked from here
plat/rockchip/rk3399/drivers/pmu/pmu_fw.S:14: Error: unable to include `./'
plat/rockchip/rk3399/drivers/pmu/pmu_fw.S:20: Info: macro invoked from here
plat/rockchip/rk3399/drivers/pmu/pmu_fw.S:14: Error: junk at end of line, first unrecognized character is `/'
plat/rockchip/rk3399/drivers/pmu/pmu_fw.S:21: Info: macro invoked from here
plat/rockchip/rk3399/drivers/pmu/pmu_fw.S:14: Error: unable to include `./'
plat/rockchip/rk3399/drivers/pmu/pmu_fw.S:21: Info: macro invoked from here
"""

Considering that the symbol is defined with escaped quotes, it is
probably safe to remove the double quotes around the INBCIN macro
parameter, so let's do that to make both compilers happy.

Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Change-Id: Id18b0341353ffc00e44e2d3c643ccdd05cc20c4f

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fix(rk3399): mark INCBIN-generated sections as SHF_ALLOC

When assembling with Clang, sections generated via the `INCBIN` macro
are not assigned the `SHF_ALLOC` attribute, and the linker therefore
do

fix(rk3399): mark INCBIN-generated sections as SHF_ALLOC

When assembling with Clang, sections generated via the `INCBIN` macro
are not assigned the `SHF_ALLOC` attribute, and the linker therefore
does not know to include them in the binary.

This change is simple: explicitly tell the assembler that the section
should have the `SHF_ALLOC` attribute.

For reference: https://man7.org/linux/man-pages/man5/elf.5.html

> SHF_ALLOC
> This section occupies memory during process execution. Some
> control sections do not reside in the memory image of an object
> file. This attribute is off for those sections.

Change-Id: I626162eae9030b5ffbd03af2be76f89a248af9ca
Signed-off-by: Chris Kay <chris.kay@arm.com>
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>

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Merge changes from topic "clang-rockchip" into integration

* changes:
build(rk3399): m0: Makefile: respect verbosity for linkerfile
build(rk3399): m0: fail linker and assembler on warnings
bui

Merge changes from topic "clang-rockchip" into integration

* changes:
build(rk3399): m0: Makefile: respect verbosity for linkerfile
build(rk3399): m0: fail linker and assembler on warnings
build(rk3399): m0: remove redundant M0_CROSS_COMPILE
feat(build): rk3399: m0: add support for new binutils versions
fix(rk3399): m0: Makefile: fix outside array bounds warning
refactor(rk3399): m0: Makefile: use same tools as in build_macros.mk
refactor(rk3399): m0: Makefile: specify ARCH to be rk3399-m0
fix(rk3588): pmu: fix assembly symbol redefinition
fix(rockchip): pmu: Do not mark already defined functions as weak
fix(rk3399): dram: Fix build with gcc 11
fix(rk3288): remove unused function
fix(px30): remove unused function

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Merge "fix(romlib): romlib build without MbedTLS" into integration

Merge "feat(tc): initialize MHU channels with RSE" into integration

Merge "fix(tc): map mem_protect flash region" into integration

feat(stm32mp2): add a runtime service for STGEN configuration

Other component such as OP-TEE may have the responsibility for
STGEN configuration but updating Arm CNTFRQ can only be done from
EL3. Th

feat(stm32mp2): add a runtime service for STGEN configuration

Other component such as OP-TEE may have the responsibility for
STGEN configuration but updating Arm CNTFRQ can only be done from
EL3. Therefore, implement a SiP SMC handler for this purpose and
a runtime service to catch SIP SMCs.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: I7854e1ae6328f149798b43d52bb1ecdf71a5aa69

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feat(stm32mp2): add common SMC runtime services

Implement the common SMC runtime services for stm32mp2 platforms.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Max

feat(stm32mp2): add common SMC runtime services

Implement the common SMC runtime services for stm32mp2 platforms.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: I214e4b2bfba439572c079bbc9ffb62bc87793ce9

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feat(stm32mp1): rework SVC services

Having two generations of STM32MPX using the same SMCCC protocol,
rework the SVC services setup to put in common what can be put
in common and implement platform-

feat(stm32mp1): rework SVC services

Having two generations of STM32MPX using the same SMCCC protocol,
rework the SVC services setup to put in common what can be put
in common and implement platform-specific handlers.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I000573e50d55dc70163c2657c12cc84085416f6b

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Merge changes Ib1b810df,I5492bab5 into integration

* changes:
feat(tc): add dsu pmu node for TC4
feat(tc): enable DSU PMU el1 access for TC4

Merge "feat(qti): platform support for qcs615" into integration

feat(qti): platform support for qcs615

Change-Id: Ibbe78a196d77530fa9d94d7d12b2f08a4b66d62e
Signed-off-by: Amarinder Singh Sethi <quic_assethi@quicinc.com>

feat(fpmr): disable FPMR trap

This patch enables support of FEAT_FPMR by enabling access
to FPMR register. It achieves it by setting the EnFPM bit of
SCR_EL3. This feature is currently enabled for N

feat(fpmr): disable FPMR trap

This patch enables support of FEAT_FPMR by enabling access
to FPMR register. It achieves it by setting the EnFPM bit of
SCR_EL3. This feature is currently enabled for NS world only.

Reference:
https://developer.arm.com/documentation/109697/2024_09/
Feature-descriptions/The-Armv9-5-architecture-extension?lang=en

Change-Id: I580c409b9b22f8ead0737502280fb9093a3d5dd2
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>

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fix(psa): increase psa-mbedtls heap size for rsa

The value assigned for the mbedtls heap size for large
rsa keys was too small when PSA_CRYPTO is set to 1,
leading to run-time failures if one was to

fix(psa): increase psa-mbedtls heap size for rsa

The value assigned for the mbedtls heap size for large
rsa keys was too small when PSA_CRYPTO is set to 1,
leading to run-time failures if one was to attempt
to use a large RSA key with PSA_CRYPTO=1.

Change-Id: Id9b2648ae911879f483f1b88301f28694af0721d
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

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Merge "feat(intel): add support for query SDM config error and status" into integration

fix(tc): map mem_protect flash region

TC platform was missing this region's mapping in its plat_arm_mmap
structure causing a data abort when trying to access it.

Signed-off-by: Jackson Cooper-Drive

fix(tc): map mem_protect flash region

TC platform was missing this region's mapping in its plat_arm_mmap
structure causing a data abort when trying to access it.

Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: I0a6322685f1ee017b0f0cfa795abac0524c13287

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feat(tc): initialize MHU channels with RSE

Initialize MHU channels between TF-A and RSE, this is a preparation
for later sending messages to RSE.

Signed-off-by: Leo Yan <leo.yan@arm.com>
Signed-off

feat(tc): initialize MHU channels with RSE

Initialize MHU channels between TF-A and RSE, this is a preparation
for later sending messages to RSE.

Signed-off-by: Leo Yan <leo.yan@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: I66095cafcc1d48249cf957a49dc1dad3059a0010

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feat(tc): enable DSU PMU el1 access for TC4

Enable DSU PMU EL1 access for TC4 to use DSU PMU using perf
in Linux.

Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen Zeyada <

feat(tc): enable DSU PMU el1 access for TC4

Enable DSU PMU EL1 access for TC4 to use DSU PMU using perf
in Linux.

Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: I5492bab5c95d60ffaaede4606d8d75c00f988eb6

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feat(mt8196): enable DP and eDP for mt8196

- Add register definitions for DP
- Add mmap entry for DP register access

Change-Id: I22ed9fa36a7e13fcaed0c137d0e8f4449b6a52d7
Signed-off-by: Mac Shen <ma

feat(mt8196): enable DP and eDP for mt8196

- Add register definitions for DP
- Add mmap entry for DP register access

Change-Id: I22ed9fa36a7e13fcaed0c137d0e8f4449b6a52d7
Signed-off-by: Mac Shen <mac.shen@mediatek.com>

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fix(versal-net): remove_redundant_lock_defs

HW_ASSISTED_COHERENCY is always enabled on cortex a78
based versal-net platform.
hence remove the redundant definitions for pm_client_lock_get
and pm_clie

fix(versal-net): remove_redundant_lock_defs

HW_ASSISTED_COHERENCY is always enabled on cortex a78
based versal-net platform.
hence remove the redundant definitions for pm_client_lock_get
and pm_client_lock_release.

Change-Id: Ifcf1bca0d494cfeb4ca23f6c884dfa5a347f786b
Signed-off-by: Amit Nagal <amit.nagal@amd.com>

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refactor(mbedtls): rename default mbedtls confs

Change the name of these confs to be version agnostic,
we will later use these configs to enforce the mbedtls
minimum version

Change-Id: I1f665c24718

refactor(mbedtls): rename default mbedtls confs

Change the name of these confs to be version agnostic,
we will later use these configs to enforce the mbedtls
minimum version

Change-Id: I1f665c2471877ecc833270c511749ff845046f10
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

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