Merge "fix(mediatek): covert MTK_BL to uppercase for the build" into integration

fix(zynqmp): modify function to have single return

This corrects the MISRA violation C2012-15.5:
A function should have a single point of exit at the end.
Introduced a temporary variable to store th

fix(zynqmp): modify function to have single return

This corrects the MISRA violation C2012-15.5:
A function should have a single point of exit at the end.
Introduced a temporary variable to store the return value to
ensure single return for the function.

Change-Id: Ibff3df16b4c591384467771bc7cb316f1773f1ea
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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fix(versal2): update DDR address map

Update DDR address map of BL32, BL33 and transfer list to support
AMD Versal Gen 2 platform's new memory map.

Change-Id: I757b2f67270034c8a3140e4bb0ac4d7e88b5d0

fix(versal2): update DDR address map

Update DDR address map of BL32, BL33 and transfer list to support
AMD Versal Gen 2 platform's new memory map.

Change-Id: I757b2f67270034c8a3140e4bb0ac4d7e88b5d055
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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fix(mediatek): covert MTK_BL to uppercase for the build

The build macro no longer coverts variable names to uppercase.
We need to convert it to uppercase to pass it on.

Change-Id: If808fc77bce71d57

fix(mediatek): covert MTK_BL to uppercase for the build

The build macro no longer coverts variable names to uppercase.
We need to convert it to uppercase to pass it on.

Change-Id: If808fc77bce71d575e2d43ff83c4d9bcdcc52326
Signed-off-by: Gavin Liu <gavin.liu@mediatek.com>

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feat(mops): enable FEAT_MOPS in EL3 when INIT_UNUSED_NS_EL2=1

FEAT_MOPS, mandatory from Arm v8.8, is typically managed in EL2.
However, in configurations where NS_EL2 is not enabled,
EL3 must set th

feat(mops): enable FEAT_MOPS in EL3 when INIT_UNUSED_NS_EL2=1

FEAT_MOPS, mandatory from Arm v8.8, is typically managed in EL2.
However, in configurations where NS_EL2 is not enabled,
EL3 must set the HCRX_EL2.MSCEn bit to 1 to enable the feature.

This patch ensures FEAT_MOPS is enabled by setting HCRX_EL2.MSCEn to 1.

Change-Id: Ic4960e0cc14a44279156b79ded50de475b3b21c5
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>

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build: remove Windows compatibility layer

For a couple of releases now we have officially withdrawn support for
building TF-A on Windows using the native environment, relying instead
on POSIX emulat

build: remove Windows compatibility layer

For a couple of releases now we have officially withdrawn support for
building TF-A on Windows using the native environment, relying instead
on POSIX emulation layers like MSYS2, Mingw64, Cygwin or WSL.

This change removes the remainder of the OS compatibility layer
entirely, and migrates the build system over to explicitly relying on a
POSIX environment.

Change-Id: I8fb60d998162422e958009afd17eab826e3bc39b
Signed-off-by: Chris Kay <chris.kay@arm.com>

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feat(s32g274a): split early clock initialization

Initializing all early clocks before the MMU is enabled can impact boot
time. Therefore, splitting the setup into A53 clocks and peripheral
clocks ca

feat(s32g274a): split early clock initialization

Initializing all early clocks before the MMU is enabled can impact boot
time. Therefore, splitting the setup into A53 clocks and peripheral
clocks can be beneficial, with the peripheral clocks configured after
fully initializing the MMU.

Change-Id: I19644227b66effab8e2c43e64e057ea0c8625ebc
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(s32g274a): enable MMU for BL31 stage

Enable the MMU and add two entries to map the BL31 code and data
regions. Additional mappings will be added dynamically, enhancing
flexibility and modularit

feat(s32g274a): enable MMU for BL31 stage

Enable the MMU and add two entries to map the BL31 code and data
regions. Additional mappings will be added dynamically, enhancing
flexibility and modularity during the porting process.

Change-Id: I333c34c58274a115f62f54730bba5b71165e3e36
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(s32g274a): dynamically map GIC regions

Dynamically add entries for the GIC distributor and all its
redistributors for the cases when the platform is booted using enabled
MMU.

Change-Id: Ia810e

feat(s32g274a): dynamically map GIC regions

Dynamically add entries for the GIC distributor and all its
redistributors for the cases when the platform is booted using enabled
MMU.

Change-Id: Ia810ec2329993057173e8fc25620a3df59b1e55d
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(s32g274a): enable MMU for BL2 stage

Enable the MMU and add two entries to map the BL2 code and data regions.
Additional mappings will be added dynamically, enhancing flexibility and
modularity

feat(s32g274a): enable MMU for BL2 stage

Enable the MMU and add two entries to map the BL2 code and data regions.
Additional mappings will be added dynamically, enhancing flexibility and
modularity during the porting process.

Change-Id: I107abf944dfdce9dcff47b08272a5001484de8a9
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(s32g274a): dynamically map siul2 and fip img

Dynamically map the remaining regions part of the BL2 stages using
dynamic regions.

Change-Id: Ia81666920b941218ddaa7d3244dfa5212525c75d
Signed-off

feat(s32g274a): dynamically map siul2 and fip img

Dynamically map the remaining regions part of the BL2 stages using
dynamic regions.

Change-Id: Ia81666920b941218ddaa7d3244dfa5212525c75d
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(s32g274a): map each image before its loading

The regions used by the stages loaded by BL2 must be mapped before they
can be used.

Change-Id: Ia70f8c5f35d7930e2b20f1a26be0ad2cdfea2b1a
Signed-of

feat(s32g274a): map each image before its loading

The regions used by the stages loaded by BL2 must be mapped before they
can be used.

Change-Id: Ia70f8c5f35d7930e2b20f1a26be0ad2cdfea2b1a
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(s32g274a): increase the number of MMU regions

Increase the maximum number of regions allocated by the translation
table library to accommodate the entries added in the next commits.

Change-Id:

feat(s32g274a): increase the number of MMU regions

Increase the maximum number of regions allocated by the translation
table library to accommodate the entries added in the next commits.

Change-Id: Ib0dd2d0dbc9b4a574367141a7c96d76dd08e2c7f
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(s32g274a): add console mapping

Add on-demand mapping of the console registers.

Change-Id: I146af2306f167602710c57b637deb1845fd95aff
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.

feat(s32g274a): add console mapping

Add on-demand mapping of the console registers.

Change-Id: I146af2306f167602710c57b637deb1845fd95aff
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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perf(psci): pass my_core_pos around instead of calling it repeatedly

On some platforms plat_my_core_pos is a nontrivial function that takes a
bit of time and the compiler really doesn't like to inli

perf(psci): pass my_core_pos around instead of calling it repeatedly

On some platforms plat_my_core_pos is a nontrivial function that takes a
bit of time and the compiler really doesn't like to inline. In the PSCI
library, at least, we have no need to keep repeatedly calling it and we
can instead pass it around as an argument. This saves on a lot of
redundant calls, speeding the library up a bit.

Change-Id: I137f69bea80d7cac90d7a20ffe98e1ba8d77246f
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(mediatek): add gic driver

Add GIC driver for taking interrupts to core.

Signed-off-by: Runyang Chen <runyang.chen@mediatek.com>
Change-Id: Id4d702b8579488befc1a1b6d37e66287dd534798

Merge "fix(intel): handle cold reset via physical reset switch" into integration

Merge changes from topic "hob_creation_in_tf_a" into integration

* changes:
feat(el3_spmc): ffa error handling in direct msg
feat(ff-a): support FFA_MSG_SEND_DIRECT_REQ2/RESP2
feat(ff-a): add

Merge changes from topic "hob_creation_in_tf_a" into integration

* changes:
feat(el3_spmc): ffa error handling in direct msg
feat(ff-a): support FFA_MSG_SEND_DIRECT_REQ2/RESP2
feat(ff-a): add FFA_MEM_PERM_GET/SET_SMC64
feat(el3-spmc): support Hob list to boot S-EL0 SP
feat(synquacer): add support Hob creation
fix(fvp): exclude extend memory map TZC regions
feat(fvp): add StandaloneMm manifest in fvp
feat(spm): use xfer list with Hob list in SPM_MM

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Merge "feat(mt8196): link prebuilt library" into integration

Merge "feat(mt8196): add Mediatek EMI stub implementation for mt8196" into integration

fix(intel): update warm reset routine and bootscratch register usage

Agilex5 platform:
Boot scratch COLD6 register is meant for Customer use only.
So, use Intel specific COLD3 register with [5:2]bit

fix(intel): update warm reset routine and bootscratch register usage

Agilex5 platform:
Boot scratch COLD6 register is meant for Customer use only.
So, use Intel specific COLD3 register with [5:2]bits to
determine the warm reset and SMP boot requests.
Also handle the unaligned DEVICE/IO memory store and load
in the assembly entrypoint startup code.

Agilex, Stratix10, N5X platforms:
Use only the LSB 4bits [3:0] of the boot scratch COLD6 register
to detect the warm reset request.

Change-Id: I4fd6e63fe0bd42ddcb4a3f81c7a7295bdc8ca65f
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): update debug messages to appropriate class

Update debug messages to VERBOSE class wherever required.

Change-Id: I44ea6b660581285290f54a507dd1131d26be2ec8
Signed-off-by: Girisha Dengi <g

fix(intel): update debug messages to appropriate class

Update debug messages to VERBOSE class wherever required.

Change-Id: I44ea6b660581285290f54a507dd1131d26be2ec8
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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feat(mt8196): link prebuilt library

If MTKLIB_PATH is provided, the build will use the library provided by
MTKLIB_PATH. Otherwise, it will use stub implementation.

Change-Id: I218e724231c8bbc6cc851

feat(mt8196): link prebuilt library

If MTKLIB_PATH is provided, the build will use the library provided by
MTKLIB_PATH. Otherwise, it will use stub implementation.

Change-Id: I218e724231c8bbc6cc851a240c6bbc4f6f49f154
Signed-off-by: Gavin Liu <gavin.liu@mediatek.corp-partner.google.com>

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refactor(tc): rename TC_FPGA_ANDROID_IMG_IN_RAM

Rename TC_FPGA_ANDROID_IMG_IN_RAM to TC_FPGA_FS_IMG_IN_RAM
to use it for debian loading to ram as well.

Change-Id: I70b68b06501d17dcebbe78bee8fec0a70

refactor(tc): rename TC_FPGA_ANDROID_IMG_IN_RAM

Rename TC_FPGA_ANDROID_IMG_IN_RAM to TC_FPGA_FS_IMG_IN_RAM
to use it for debian loading to ram as well.

Change-Id: I70b68b06501d17dcebbe78bee8fec0a701106c92
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>

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Merge changes from topic "handoff_tpm_event_log" into integration

* changes:
feat(qemu): hand off TPM event log via TL
feat(handoff): common API for TPM event log handoff
feat(handoff): transf

Merge changes from topic "handoff_tpm_event_log" into integration

* changes:
feat(qemu): hand off TPM event log via TL
feat(handoff): common API for TPM event log handoff
feat(handoff): transfer entry ID for TPM event log
fix(qemu): fix register convention in BL31 for qemu
fix(handoff): fix register convention in opteed

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