| c00baeec | 27-Nov-2020 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
plat:xilinx:zynqmp: Add JTAG DCC support
As per the new multi-console framework, updating the JTAG DCC support.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Acked-by: Mic
plat:xilinx:zynqmp: Add JTAG DCC support
As per the new multi-console framework, updating the JTAG DCC support.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I62cfbb57ae7e454fbc91d1c54aafa6e99f9a35c8
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| 4697164a | 26-Feb-2021 |
Tejas Patel <tejas.patel@xilinx.com> |
plat: xilinx: versal: Mark IPI calls secure/non-secure
BIT24 of IPI command header is used to determine if caller is
secure or non-secure.
Mark BIT24 of IPI command header as non-secure if SMC call
plat: xilinx: versal: Mark IPI calls secure/non-secure
BIT24 of IPI command header is used to determine if caller is
secure or non-secure.
Mark BIT24 of IPI command header as non-secure if SMC caller
is non-secure.
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: Iec25af8f4b202093f58e858ee47cd9cd46890267
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| 0888fcf2 | 18-Mar-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "plat: xilinx: versal: Remove cortex-a53 compilation" into integration |
| 0fb73638 | 18-Mar-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "plat: xilinx: Add timeout while waiting for IPI Ack" into integration |
| 4a7b060b | 16-Mar-2021 |
Michal Simek <michal.simek@xilinx.com> |
plat: xilinx: versal: Remove cortex-a53 compilation
Versal is a72 based that's why there is no reason to build low level
assemble code for a53.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
plat: xilinx: versal: Remove cortex-a53 compilation
Versal is a72 based that's why there is no reason to build low level
assemble code for a53.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: Iff9cf2582102d951825b87fd9af18e831ca717d6
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| 1b7e5ca9 | 03-Mar-2021 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
plat: xilinx: zynqmp: Add missing ids for 43/46/47dr devices
Add support for ZU43DR, ZU46DR and ZU47DR to the list of zynqmp
devices. The ZU43DR, ZU46DR and ZU47DR RFSoC silicon id values are
0x7d,
plat: xilinx: zynqmp: Add missing ids for 43/46/47dr devices
Add support for ZU43DR, ZU46DR and ZU47DR to the list of zynqmp
devices. The ZU43DR, ZU46DR and ZU47DR RFSoC silicon id values are
0x7d, 0x78 and 0x7f.
Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@xilinx.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I566f707116d83475de7c87a6004ca96bf7bccebe
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| 4d9b9b23 | 25-Feb-2021 |
Tejas Patel <tejas.patel@xilinx.com> |
plat: xilinx: Add timeout while waiting for IPI Ack
Return timeout error if, IPI is not acked in specified timeout.
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Change-Id: I27be3d4d4eb5bc57f
plat: xilinx: Add timeout while waiting for IPI Ack
Return timeout error if, IPI is not acked in specified timeout.
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Change-Id: I27be3d4d4eb5bc57f6a84c839e2586278c0aec19
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| 830774bf | 24-Jan-2021 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
plat:xilinx:zynqmp: Remove the custom crash implementation
Removing the custom crash implementation and use
plat/common/aarch64/crash_console_helpers.S.
Signed-off-by: Venkatesh Yadav Abbarapu <ven
plat:xilinx:zynqmp: Remove the custom crash implementation
Removing the custom crash implementation and use
plat/common/aarch64/crash_console_helpers.S.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I045d42eb62bcaf7d1e18fbe9ab9fb9470e800215
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| f621d5fb | 20-Jan-2021 |
Rajan Vaja <rajan.vaja@xilinx.com> |
plat: xilinx: versal: Remove code duplication
Some switch cases uses same operation. So, club switch cases
which uses same operation and remove duplicate code.
Signed-off-by: Rajan Vaja <rajan.vaja
plat: xilinx: versal: Remove code duplication
Some switch cases uses same operation. So, club switch cases
which uses same operation and remove duplicate code.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I260b474c0ff3f2ca102c32d4af2e4abba2b8f57c
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| 0a67923b | 23-Nov-2020 |
Will Wong <willw@xilinx.com> |
zynqmp: pm: Add support for PS and system reset on WDT restart
Add ability to support PS and System reset after idling the APU,
by reading the restart scope from the PMU.
Signed-off-by: Will Wong <
zynqmp: pm: Add support for PS and system reset on WDT restart
Add ability to support PS and System reset after idling the APU,
by reading the restart scope from the PMU.
Signed-off-by: Will Wong <willw@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I23c01725d8ebb71ad34be02ab204411b93620702
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| 19fe3c72 | 05-Oct-2018 |
Rajan Vaja <rajan.vaja@xilinx.com> |
zynqmp: pm: Update PM version and support PM version check
ATF is not checking PM version. Add version check in such
a way that it is compatible with current and newer version
of PM.
Signed-off-by:
zynqmp: pm: Update PM version and support PM version check
ATF is not checking PM version. Add version check in such
a way that it is compatible with current and newer version
of PM.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: Ia095d118121e6f75e8d320e87d5e2018068fa079
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| e43258fa | 11-Jan-2021 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
plat: xilinx: Fix non-MISRA compliant code
This patch fixes the non compliant code like missing braces for
conditional single statement bodies.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.ab
plat: xilinx: Fix non-MISRA compliant code
This patch fixes the non compliant code like missing braces for
conditional single statement bodies.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I95b410ae5950f85dc913c4448fcd0a97e0fd490c
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| 24ca0fa6 | 06-Jan-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "xilinx-sd-tap-delay" into integration
* changes:
plat: zynqmp: Disable ITAPDLYENA bit for zero ITAP delay
plat: zynqmp: Check for DLL status before doing reset |
| 504925f9 | 23-Nov-2020 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
xilinx: zynqmp: Add support for Error Management
Adding the EM specific smc handler for the EM-related requests.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Signed-off-b
xilinx: zynqmp: Add support for Error Management
Adding the EM specific smc handler for the EM-related requests.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I98122d49604a01a2f6bd1e509a5896ee68069dd0
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| 1f910194 | 23-Nov-2020 |
VNSL Durga <vnsl.durga.challa@xilinx.com> |
zynqmp:pm: Adds new zynqmp-pm api SMC call for efuse
This patch adds new api to access zynqmp efuse memory
Signed-off-by: VNSL Durga <vnsl.durga.challa@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.
zynqmp:pm: Adds new zynqmp-pm api SMC call for efuse
This patch adds new api to access zynqmp efuse memory
Signed-off-by: VNSL Durga <vnsl.durga.challa@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I0971ab6549552a6f96412431388d19b822db00ab
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| d716f045 | 23-Nov-2020 |
Kalyani Akula <kalyania@xilinx.com> |
zynqmp : pm : Adds new zynqmp-pm api SMC call for register access
This patch adds new zynqmp-pm api to provide read/write access to
CSU or PMU global registers.
Signed-off-by: Kalyani Akula <kalyan
zynqmp : pm : Adds new zynqmp-pm api SMC call for register access
This patch adds new zynqmp-pm api to provide read/write access to
CSU or PMU global registers.
Signed-off-by: Kalyani Akula <kalyania@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I4fd52eb732fc3e6a8bccd96cad7dc090b2161042
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| 95c3ebcb | 23-Nov-2020 |
Mirela Simonovic <mirela.simonovic@aggios.com> |
zynqmp: pm: Reimplement pinctrl get/set config parameter EEMI API calls
Functions are reimplemented to issue system-level pinctrl EEMI calls
to the PMU-FW rather than using MMIO read/write. Macros a
zynqmp: pm: Reimplement pinctrl get/set config parameter EEMI API calls
Functions are reimplemented to issue system-level pinctrl EEMI calls
to the PMU-FW rather than using MMIO read/write. Macros and functions
that appear to be unused after the change is made are removed.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I51f2285a79f202cb2ca9f031044002e16dd1e92f
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| 10a346d9 | 13-Sep-2018 |
Mirela Simonovic <mirela.simonovic@aggios.com> |
zynqmp: pm: Reimplement pinctrl set/get function EEMI API
Functions are reimplemented to issue system-level pinctrl EEMI calls
to the PMU-FW rather than using MMIO read/write. Macros and functions
t
zynqmp: pm: Reimplement pinctrl set/get function EEMI API
Functions are reimplemented to issue system-level pinctrl EEMI calls
to the PMU-FW rather than using MMIO read/write. Macros and functions
that appear to be unused after the change is made are removed.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I21b8fda855aa69090b85d6aaf411e19560201cb5
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| 43a029cb | 13-Sep-2018 |
Mirela Simonovic <mirela.simonovic@aggios.com> |
zynqmp: pm: Implement pinctrl request/release EEMI API
The calls are just passed through to the PMU-FW. Before issuing
other pinctrl functions the pin should be successfully requested.
Signed-off-b
zynqmp: pm: Implement pinctrl request/release EEMI API
The calls are just passed through to the PMU-FW. Before issuing
other pinctrl functions the pin should be successfully requested.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: Ibce280edebedf779b3962009c274d0b3d928e0e4
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| 4b310108 | 24-Nov-2020 |
Rajan Vaja <rajan.vaja@xilinx.com> |
zynqmp: pm: Update return type in query functions
In pm_query_data() function return type is stored in response so
there is no use of return type. Update return type of function
pm_query_data() from
zynqmp: pm: Update return type in query functions
In pm_query_data() function return type is stored in response so
there is no use of return type. Update return type of function
pm_query_data() from enum pm_ret_status to void. Similarly
update return type of pm_api_clock_get_name() and
pm_api_pinctrl_get_function_name() functions.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: Id811926f0b4ebcc472480bb94f3b88109eb036cd
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| fe1fa205 | 30-Oct-2020 |
Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> |
plat: zynqmp: Disable ITAPDLYENA bit for zero ITAP delay
This patch disable the ITAPDLYENA bit for ITAP delay value zero.
As per IP design, it is recommended to disable the ITAPDLYENA bit
before aut
plat: zynqmp: Disable ITAPDLYENA bit for zero ITAP delay
This patch disable the ITAPDLYENA bit for ITAP delay value zero.
As per IP design, it is recommended to disable the ITAPDLYENA bit
before auto-tuning.
Also disable OTAPDLYENA bit always as there is one issue in RTL
where SD0_OTAPDLYENA has been wrongly connected to both SD0 and SD1
controllers. Hence it is recommended to disable OTAPDLYENA bit always
for both the controllers.
Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
Acked-by: Srinivas Goud <srinivas.goud@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: Icf035cb63510ac7bec4e9d523a622f145eaf0989
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| 2ab0ef8d | 20-Oct-2020 |
Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> |
plat: zynqmp: Check for DLL status before doing reset
This patch check for the DLL status before doing the DLL reset.
If DLL reset is already issued then skip the reset inside ATF
otherwise DLL rese
plat: zynqmp: Check for DLL status before doing reset
This patch check for the DLL status before doing the DLL reset.
If DLL reset is already issued then skip the reset inside ATF
otherwise DLL reset will be issued.
By doing this way, all the following cases will be supported.
1. Patched ATF + Patched Linux base.
2. Older ATF + Patched Linux base.
3. Patched ATF + Older Linux base.
Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I53a0a27521330f1543275cc9cb44cd1dfc569c65
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| a82b5f70 | 10-Dec-2020 |
Manish Pandey <manish.pandey2@arm.com> |
xilinx: versal: fix static failure
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Icef550072296d6aba89a0827dd72d0b86047556f |
| 852e4940 | 09-Dec-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "versal-bug-fixes-and-new-apis" into integration
* changes:
plat: xilinx: versal: Add support of register notifier
plat: xilinx: versal: Add support to get clock rate va
Merge changes from topic "versal-bug-fixes-and-new-apis" into integration
* changes:
plat: xilinx: versal: Add support of register notifier
plat: xilinx: versal: Add support to get clock rate value
plat: xilinx: versal: Add support of set max latency for the device
plat: versal: Add InitFinalize API call
xilinx: versal: Updated Response of QueryData API call
plat:xilinx:versal: Use defaults when PDI is without sw partitions
plat: xilinx: Mask unnecessary bytes of return error code
xilinx: versal: Skip store/restore of GIC during CPU idle
plat: versal: Update API list in feature check
xilinx: versal: Do not pass ACPU0 always in set_wakeup_source()
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| c8f62536 | 18-Sep-2018 |
Ravi Patel <ravi.patel@xilinx.com> |
zynqmp: pm: Update flags in common clk divisor node
Current implementation doesn't support change of div1 value if clk
has 2 divisor because div1 clk is the parent of the div2 clk and div2
clk does
zynqmp: pm: Update flags in common clk divisor node
Current implementation doesn't support change of div1 value if clk
has 2 divisor because div1 clk is the parent of the div2 clk and div2
clk does not have SET_RATE_PARENT flag.
This causes div1 value to be fixed and only value of div2 will be
adjusted according to required clock rate.
Example:
Consider a case of nand_ref clock which has 2 divisor and 1 mux.
The frequency of mux clock is 1500MHz and default value of div1 and
div2 is 15 and 1 respectively. So the final clock will be of 100MHz.
When driver requests 80MHz for nand_ref clock, clock framework will
adjust the div2 value to 1 (setting div2 value 2 results final clock
to 50MHz which is more inaccurate compare to 100Mhz) which results
final clock to 100MHz.
Ideally the value of div1 and div2 should be updated to 19 and 1
respectively so that final clock goes to around 78MHz.
This patch fixes above problem by allowing change in div1 value.
Signed-off-by: Ravi Patel <ravi.patel@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: Ibb98f6748d28653fdd1e59bf433b6a37ce9c1a58
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