Merge "fix(xilinx): warn if reserved memory pre-exists in DT" into integration

Merge "fix(versal): kernel QEMU boot is failing on versal platform" into integration

fix(xilinx): warn if reserved memory pre-exists in DT

Memory reservation for tf-a does not happen in
runtime if memory reservation node pre-exists in DT.
Presence of reserved area is checked and use

fix(xilinx): warn if reserved memory pre-exists in DT

Memory reservation for tf-a does not happen in
runtime if memory reservation node pre-exists in DT.
Presence of reserved area is checked and user is
warned if it pre-exists.

Change-Id: I50e18be942777747e9074bb9d8e0305a29c28178
Signed-off-by: Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>

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feat(versal): add support for QEMU COSIM platform

QEMU COSIM introduces a new platform id for Versal Platform.
QEMU COSIM is equivalent to QEMU with additional COSIM
extensions, so just switching pl

feat(versal): add support for QEMU COSIM platform

QEMU COSIM introduces a new platform id for Versal Platform.
QEMU COSIM is equivalent to QEMU with additional COSIM
extensions, so just switching platform_id to QEMU if QEMU COSIM
id is detected.

Change-Id: If81e0bf04301c7101f89d0df13134f7d04e8c257
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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fix(versal): kernel QEMU boot is failing on versal platform

Due to deprecation of VERSAL_PLATFORM build argument,
the board detection is done at runtime due to this the cpu
and uart clock freq was n

fix(versal): kernel QEMU boot is failing on versal platform

Due to deprecation of VERSAL_PLATFORM build argument,
the board detection is done at runtime due to this the cpu
and uart clock freq was not set as required to silicon values.

Updated Versal QEMU cpu_clock and uart_clock to silicon values.

Change-Id: I7c772f07ba45eb7e0ae095fd670718190e24f0d7
Signed-off-by: Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>

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fix(xilinx): map PMC_GPIO device node to interrupt for wakeup source

Currently, PMC_GPIO device node was not mapped with interrupt number
during the setup of wakeup source while suspending. As a res

fix(xilinx): map PMC_GPIO device node to interrupt for wakeup source

Currently, PMC_GPIO device node was not mapped with interrupt number
during the setup of wakeup source while suspending. As a result,
system cannot resume using PMC_GPIO as wakeup source.

To address this issue, add an entry for PMC_GPIO node to map with its
corresponding interrupt number.

Change-Id: Ic681b7b2e7c0b3bd542c8e4664a2129e4b91c459
Signed-off-by: Ronak Jain <ronak.jain@amd.com>

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fix(xilinx): optimize logic to read IPI response

Optimize logic to read IPI response from firmware and avoid using
temporary buffer. Also, use pointer instead of array as per standard
format to pass

fix(xilinx): optimize logic to read IPI response

Optimize logic to read IPI response from firmware and avoid using
temporary buffer. Also, use pointer instead of array as per standard
format to pass by reference in function.

Change-Id: I45ebaeacc932a11bbfd4b7d9b9c43b4ee8ee7df2
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>

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Merge "fix(zynqmp): handle secure SGI at EL1 for OP-TEE" into integration

fix(xilinx): fix OVERRUN coverity violation

This change fixes below MISRA violation:
CID 441243: Memory - corruptions (OVERRUN)
Overrunning callee's array of size 7 by passing argument "7UL" in ca

fix(xilinx): fix OVERRUN coverity violation

This change fixes below MISRA violation:
CID 441243: Memory - corruptions (OVERRUN)
Overrunning callee's array of size 7 by passing argument "7UL" in call to
"pm_ipi_send_sync".

Change-Id: Ie7fd9ccad058e97eb4b36c4f0e77be8bfb3e6006
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>

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Merge "fix(versal2): add ufs specific features support" into integration

Merge "feat(versal): deprecate build time arg VERSAL_PLATFORM" into integration

fix(versal2): add ufs specific features support

Following IOCTL IDs are required for UFS specific functionalities.

IOCTL ID - 40(IOCTL_UFS_TXRX_CFGRDY_GET)
This gives the Tx_Rx_config_rdy_signal_mo

fix(versal2): add ufs specific features support

Following IOCTL IDs are required for UFS specific functionalities.

IOCTL ID - 40(IOCTL_UFS_TXRX_CFGRDY_GET)
This gives the Tx_Rx_config_rdy_signal_mon(0xF1061054) register value
which contains the Tx and Rx lanes configuration ready signal information.

IOCTL ID - 41(IOCTL_UFS_SRAM_CSR_SEL)
Select - 0(IOCTL_UFS_SRAM_CSR_SET)
This will allow to set sram control and status register (0xF106104C)
with the value provided by driver.

Select - 1(IOCTL_UFS_SRAM_CSR_GET)
This should return the sram control and status register (0xF106104C) value
to the driver.

UFS Host reset assert/de-assert(using SCMI) support is added.
register address : 0xF1260340

UFS PHY reset assert/de-assert(using SCMI) support is added.
register address : 0xF1061050

Change-Id: I5368cc7251350946bd5ddb3a4c817b75e1d4a43e
Signed-off-by: Amit Nagal <amit.nagal@amd.com>

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feat(xilinx): add feature check function for TF-A specific APIs

Currently, there is common feature check function for firmware APIs
and TF-A specific APIs. This should be separate from firmware APIs

feat(xilinx): add feature check function for TF-A specific APIs

Currently, there is common feature check function for firmware APIs
and TF-A specific APIs. This should be separate from firmware APIs.
So add new TF-A API for feature check of TF-A specific APIs.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I5585d17fb6aa1e98989d935117cca10bdb85133e

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feat(xilinx): update SiP SVC version number

SMC ID is fixed in new SiP SVC call format while it varies according
to PLM header in old Linux. So, enhance SIP_SVC_VERSION number to
support backward co

feat(xilinx): update SiP SVC version number

SMC ID is fixed in new SiP SVC call format while it varies according
to PLM header in old Linux. So, enhance SIP_SVC_VERSION number to
support backward compatibility and to use full request and response
buffer from bare-metal or Linux.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I6764cc92b33b7366640f553827e80c5e97985fcf

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feat(xilinx): update TF-A to passthrough all PLM commands

Currently, the IDs used in PLM CMD header are mixed with SMC IDs in
TF-A which is restricting the range of IDs that can be used by PLM.
Also

feat(xilinx): update TF-A to passthrough all PLM commands

Currently, the IDs used in PLM CMD header are mixed with SMC IDs in
TF-A which is restricting the range of IDs that can be used by PLM.
Also, the SMC call from firmware driver is passing all 7 32-bit
words in request but TF-A is not passing all of them to firmware and
TF-A passes only 4 32-bit words from firmware to Linux in response.

So, update TF-A to passthrough all PLM commands by having a single
fixed SMC ID for all PLM commands and keep the PLM header in subsequent
SMC arguments. Also, enhance size of payload argument count to support
maximum payloads in request and response buffers to transmit all the
IPI command properly.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I2601caba849bce3f294177b63baa1ad688e3c5bb

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fix(xilinx): fix logic to read ipi response

Currently, PLM IPI command supports total 8 32-bit payloads. But existing
logic to read IPI response in TF-A is trying to read 9 32-bit payloads
(ret stat

fix(xilinx): fix logic to read ipi response

Currently, PLM IPI command supports total 8 32-bit payloads. But existing
logic to read IPI response in TF-A is trying to read 9 32-bit payloads
(ret status + 8 ret payloads) in case of IPI_CRC_CHECK enabled which is
incorrect.

So, fix logic to read only 8 32-bit payloads (ret status + 6 ret payloads + CRC)
in case when IPI_CRC_CHECK is enabled and read 7 32-bit payloads
(ret status + 5 ret payloads + CRC) in case when IPI_CRC_CHECK is disabled.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I0abca2f787cc7a66fdd5522e6bd15a9771029071

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feat(versal): deprecate build time arg VERSAL_PLATFORM

Update Versal platform to enable runtime detection of variants instead
of relying on the build argument VERSAL_PLATFORM.
Integrate functionalit

feat(versal): deprecate build time arg VERSAL_PLATFORM

Update Versal platform to enable runtime detection of variants instead
of relying on the build argument VERSAL_PLATFORM.
Integrate functionality for identifying the board variant during
runtime, allowing dynamic adjustment of CPU and UART clock values
accordingly.
Print the runtime board information during boot.
This advancement streamlines the build process by eliminating
dependencies on variant-specific builds, enabling the use of a single
binary for multiple variants.
Removing all the platform related constants for versal_virt,SPP,EMU as
they are not used.

Change-Id: I8c1a1d391bd1a8971addc1f56f8309a3fb75aa6d
Signed-off-by: Amey Avinash Raghatate <AmeyAvinash.Raghatate@amd.com>
Signed-off-by: Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>

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fix(zynqmp): handle secure SGI at EL1 for OP-TEE

OP-TEE requires SGIs to be handled at S-EL1. The
Makefile was not properly setting the flag
GICV2_G0_FOR_EL3 to 0 when the SPD is OP-TEE.

Change-Id:

fix(zynqmp): handle secure SGI at EL1 for OP-TEE

OP-TEE requires SGIs to be handled at S-EL1. The
Makefile was not properly setting the flag
GICV2_G0_FOR_EL3 to 0 when the SPD is OP-TEE.

Change-Id: I256afa37ddf4ad4a154c43d51807de670c3689bb
Signed-off-by: Shen Jiamin <shen_jiamin@comp.nus.edu.sg>

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feat(zynqmp): move zynqmp platform to xlat tables v2

Switch to xlat table v2 version to add support for dynamic mapping
which is not supported in xlat table v1. It can be used for run
time DT mappin

feat(zynqmp): move zynqmp platform to xlat tables v2

Switch to xlat table v2 version to add support for dynamic mapping
which is not supported in xlat table v1. It can be used for run
time DT mapping. Also xlat table v1 version is going to be
deprecated that's why switch is necessary and removed unused xlat
table v1 macro from platform.mk.
With ENABLE_LTO enabled, size difference in OCM between xlat
table v2 and xlat table v1 release is 82193 - 82058 = 135 bytes.

Change-Id: Ifec2e75fb19670e83dc761fc40a8c4cd5ed9087b
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Signed-off-by: Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>

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feat(zynqmp): enable ENABLE_LTO flag

Enabling Link Time Optimization in platform.mk for AMD-Xilinx
ZynqMP platform optimizes TF-A size.
With ENABLE_LTO=0, the release bl31.elf size is 86098.
With EN

feat(zynqmp): enable ENABLE_LTO flag

Enabling Link Time Optimization in platform.mk for AMD-Xilinx
ZynqMP platform optimizes TF-A size.
With ENABLE_LTO=0, the release bl31.elf size is 86098.
With ENABLE_LTO=1, the release bl31.elf size reduces to 81866.
The size difference in OCM is 4232 bytes, saving up to 4KB.

Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: I6d5001a9ac250e3a87b958e9b665962a917265d6

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Merge "fix(versal): remove check for bl32 load address" into integration

fix(versal): remove check for bl32 load address

With PLM firmware version 2024.1 the bl32 load address is set
correctly in handoff parameters.
Hence the check to initialize bl32 load address when bl

fix(versal): remove check for bl32 load address

With PLM firmware version 2024.1 the bl32 load address is set
correctly in handoff parameters.
Hence the check to initialize bl32 load address when bl32
load address is indicated as 0 in handoff is removed.

Change-Id: I322b8d2fc1137297142704ea1087c185e16177cc
Signed-off-by: Amit Nagal <amit.nagal@amd.com>

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fix(versal-net): remove check for bl32 load address

With PLM firmware version 2024.1 the bl32 load address is set
correctly in handoff parameters.
Hence the check to initialize bl32 load address whe

fix(versal-net): remove check for bl32 load address

With PLM firmware version 2024.1 the bl32 load address is set
correctly in handoff parameters.
Hence the check to initialize bl32 load address when bl32
load address is indicated as 0 in handoff is removed.

Change-Id: Ie927787129816e79d43ba4803f6916e20d81458a
Signed-off-by: Amit Nagal <amit.nagal@amd.com>

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feat(versal-net): set lower cluster bus qos value

arm clusterbusqos register has a default value of 0xeeeeeeee.
this may create bottleneck for other masters in system when
accessing other memories i

feat(versal-net): set lower cluster bus qos value

arm clusterbusqos register has a default value of 0xeeeeeeee.
this may create bottleneck for other masters in system when
accessing other memories including ddr.
hence clusterbusqos is setup to lowest value 0.

Change-Id: I73d55066eb84e198c8c69593bb5700745f04f290
Signed-off-by: Amit Nagal <amit.nagal@amd.com>

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fix(xilinx): handle power down event if SGI not registered

Currently, if SGI is not registered by Linux and power down event from
firmware is received then it's not getting handled in TF-A and core

fix(xilinx): handle power down event if SGI not registered

Currently, if SGI is not registered by Linux and power down event from
firmware is received then it's not getting handled in TF-A and core power
down is not happening. Because of that subsystem restart or force power
down without Linux boot is not happening. So, handle power down event in
TF-A if Linux not registered SGI.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I0c23792daba6ae47004ae99e232c77e17230bcfb

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