feat(xilinx): remove crash console unused macros

Macros are not used that's why remove them.

Change-Id: I4519ea0b9e30b757ab8a6ee3bb56af45dddc0d96
Signed-off-by: Michal Simek <michal.simek@amd.com>

feat(versal-net): remove empty crash console setup

Private plat_crash_console_init() has all the setup commented
that's why it was never been tested.
pl011 uart is supposed to be used as crash conso

feat(versal-net): remove empty crash console setup

Private plat_crash_console_init() has all the setup commented
that's why it was never been tested.
pl011 uart is supposed to be used as crash console and it should be
enought to add CONSOLE_FLAG_CRASH and remove platform specific
implementation and use generic one.
Early console can't be used for early ASM debugging but that's
expected and not required.

Change-Id: I1267fd78c0d6532a0baddbcad8a5b2a7dfc7750b
Signed-off-by: Michal Simek <michal.simek@amd.com>

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fix(versal-net): don't clear pending interrupts

All pending interrupts should be handled by their interrupt handlers. CPU
cores remain in suspend state if pending interrupts are cleared.

Signed-of

fix(versal-net): don't clear pending interrupts

All pending interrupts should be handled by their interrupt handlers. CPU
cores remain in suspend state if pending interrupts are cleared.

Signed-off-by: Saeed Nowshadi <saeed.nowshadi@amd.com>
Change-Id: Id8ddf36cbcc07484f232c477277c4da106985c8f

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fix(versal-net): make pmc ipi channel as secure

Make PMC IPI channel for Versal NET as secure so that NS
systems cannot directly access or modify secure systems.

Signed-off-by: Jay Buddhabhatti <ja

fix(versal-net): make pmc ipi channel as secure

Make PMC IPI channel for Versal NET as secure so that NS
systems cannot directly access or modify secure systems.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I75ba8796859dcb35644f3e144d7dc5926755ef78

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chore(xilinx): reorder headers in assembly files

In tf-a-ci-scripts repo, change commit 8ffa3d571b(ci(static-checks):
correct include order for *.S macro headers) provides a fix related
to header fi

chore(xilinx): reorder headers in assembly files

In tf-a-ci-scripts repo, change commit 8ffa3d571b(ci(static-checks):
correct include order for *.S macro headers) provides a fix related
to header file include order in assembly files. With the above fix,
improper header order in assembly files has been detected.

Reorder the header includes in assembly files as per the update
in tf-a-ci-scripts.

Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: I4a4f3c5bb73886dae234160b893470443f1424fc

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feat(versal-net): ddr address reservation in dtb at runtime

When the TF-A is placed in DDR memory range, the DDR memory range
needs to be explicitly reserved in the default device tree.

A new build

feat(versal-net): ddr address reservation in dtb at runtime

When the TF-A is placed in DDR memory range, the DDR memory range
needs to be explicitly reserved in the default device tree.

A new build time parameter, XILINX_OF_BOARD_DTB_ADDR, is introduced.
The TF-A will reserve the DDR memory only when a valid DTB address
is provided to XILINX_OF_BOARD_DTB_ADDR during build.

Now the user has options, either manually reserve the desired DDR
address range for TF-A in device tree or let TF-A access and modify
the device tree, to reserve the DDR address range, in runtime using
the build parameter.

Change-Id: I45a5d9a8343ea8a19ea014a70023731de94d061a
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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Merge "chore(xilinx): reorder include files as per TF-A guidelines" into integration

feat(versal-net): get the handoff params using IPI

Use the IPI command GET_HANDOFF_PARAM to get the PLM to TF-A handoff
parameters. The BL32/BL33 information from the handoff parameters will
be used

feat(versal-net): get the handoff params using IPI

Use the IPI command GET_HANDOFF_PARAM to get the PLM to TF-A handoff
parameters. The BL32/BL33 information from the handoff parameters will
be used by TF-A.

If no valid PLM to TF-A handoff parameters are available then,
the TF-A will fall back to the build time information or defaults
set in the TF-A for BL32/BL33.

Once the bootmode identification is supported the default configuration
will be done only for JTAG and for all other bootmodes PLM to TF-A
handoff parameters will be used.

Change-Id: Ia2204fe30fea6f32b4e5d2610820217e6ed23e4d
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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chore(xilinx): reorder include files as per TF-A guidelines

This commit reorders the include files in accordance with the
guidelines provided by Trusted Firmware-A (TF-A).
The include files are rear

chore(xilinx): reorder include files as per TF-A guidelines

This commit reorders the include files in accordance with the
guidelines provided by Trusted Firmware-A (TF-A).
The include files are rearranged to ensure a consistent and
organized structure in the codebase, facilitating better
readability and maintainability.

https: //trustedfirmware-a.readthedocs.io/en/latest/process/coding-style.html#headers-and-inclusion
https://git.trustedfirmware.org/ci/tf-a-ci-scripts.git/tree/script/static-checks/

For example, to run header check:
/tf-a-ci-scripts/script/static-checks/check-include-order.py --tree ${PWD} > Includefileorder.txt

Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: Ia5802722e69859596b94f31ec40755adbf7d865b

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chore(xilinx): follow kernel doc format for functional documentation

For TF-A, there is no format specified for functional documentation.
For AMD-Xilinx platforms, following kernel-doc format for th

chore(xilinx): follow kernel doc format for functional documentation

For TF-A, there is no format specified for functional documentation.
For AMD-Xilinx platforms, following kernel-doc format for the functional
documentation to make sure AMD-xilinx documentation is align with
actual code.

For example use kernel-doc from linux to call:
<linux>/scripts/kernel-doc -man -v 1 >/dev/null file...

Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: Idcc9def408b6c8da35b36f67ef82fc00890e998c

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Merge changes from topic "xlnx_smcc_soc_id" into integration

* changes:
feat(versal-net): add support for SMCC ARCH SOC ID
feat(versal): add support for SMCC ARCH SOC ID
refactor(versal-net):

Merge changes from topic "xlnx_smcc_soc_id" into integration

* changes:
feat(versal-net): add support for SMCC ARCH SOC ID
feat(versal): add support for SMCC ARCH SOC ID
refactor(versal-net): move macros to common header
feat(xilinx): add support to get chipid

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Merge changes from topic "xilinx-ipi" into integration

* changes:
feat(xilinx): fix IPI calculation for Versal/NET
feat(xilinx): setup local/remote id in header
feat(xilinx): clean macro names

Merge changes from topic "xilinx-ipi" into integration

* changes:
feat(xilinx): fix IPI calculation for Versal/NET
feat(xilinx): setup local/remote id in header
feat(xilinx): clean macro names
fix(zynqmp): do not export apu_ipi
fix(zynqmp): remove unused headers
feat(xilinx): move IPI related macros to plat_ipi.h

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Merge "feat(versal-net): add the IPI CRC checksum macro support" into integration

feat(versal-net): add support for SMCC ARCH SOC ID

Add support for SMCCC_ARCH_SOC_ID as per SMC Calling Convention for
Versal NET platform.
The SMCC ARCH SOC ID call is used by system software to ob

feat(versal-net): add support for SMCC ARCH SOC ID

Add support for SMCCC_ARCH_SOC_ID as per SMC Calling Convention for
Versal NET platform.
The SMCC ARCH SOC ID call is used by system software to obtain the SiP
defined SoC identification details.

Change-Id: I6648051c7f5fa27d2f02080209da36ee8d5a9d95
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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refactor(versal-net): move macros to common header

Move the macros to common header from platform specific folder, so that
the same macros can be re-used in other platforms.

Change-Id: I355b024f5e8

refactor(versal-net): move macros to common header

Move the macros to common header from platform specific folder, so that
the same macros can be re-used in other platforms.

Change-Id: I355b024f5e870c6fc104598bc571dbaa29503ae2
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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fix(versal-net): fix BLXX memory limits for user defined values

When compiling with user defined areas of memory the platform code
calculates the size with (base + size - 1). However, the linker
fi

fix(versal-net): fix BLXX memory limits for user defined values

When compiling with user defined areas of memory the platform code
calculates the size with (base + size - 1). However, the linker
file aligns section on a page boundary. So having the -1 in
the size calculations leads to an error message looking like this:

bl31.elf section `coherent_ram' will not fit in region `RAM'
aarch64-buildroot-linux-uclibc-ld: region `RAM' overflowed by 1 byte

While at it fix all other occurences of predefined values that were
calculated with -1.

Fixes: 1d333e69091f ("feat(versal-net): add support for Xilinx
Versal NET platform")
Change-Id: I4455f63ee3ad52369f517a7d8d3627faf0b28c0f
Signed-off-by: Michal Simek <michal.simek@amd.com>

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feat(xilinx): fix IPI calculation for Versal/NET

Fix buffer calculation logic for Versal and Versal NET to use
LOCAL/REMOTE_ID.

Change-Id: Icf6985a19183cc8e51f3a536130695e00c32c736
Signed-off-by: M

feat(xilinx): fix IPI calculation for Versal/NET

Fix buffer calculation logic for Versal and Versal NET to use
LOCAL/REMOTE_ID.

Change-Id: Icf6985a19183cc8e51f3a536130695e00c32c736
Signed-off-by: Michal Simek <michal.simek@amd.com>

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feat(xilinx): setup local/remote id in header

Use new macros IPI_LOCAL_ID/IPI_REMOTE_ID to specify source and
destination channels.

Change-Id: I558eebb4d4a83ae0ca9316824f9dba7426adbe3f
Signed-off-b

feat(xilinx): setup local/remote id in header

Use new macros IPI_LOCAL_ID/IPI_REMOTE_ID to specify source and
destination channels.

Change-Id: I558eebb4d4a83ae0ca9316824f9dba7426adbe3f
Signed-off-by: Michal Simek <michal.simek@amd.com>

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feat(xilinx): clean macro names

This is preparation for cleaning up IPI local and remote side
communication. As of today macros are aligned to communication
channel but there is missing calculation

feat(xilinx): clean macro names

This is preparation for cleaning up IPI local and remote side
communication. As of today macros are aligned to communication
channel but there is missing calculation based on channel
selection.

Change-Id: Iac7daf832ff372ea2fece72a15afdfe988b4b7db
Signed-off-by: Michal Simek <michal.simek@amd.com>

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fix(zynqmp): remove unused headers

There is no need to include all headers. Enough to have only needed one.

Change-Id: I4813156404969df36f66c1102cd627fdc1e3e9dc
Signed-off-by: Michal Simek <michal.

fix(zynqmp): remove unused headers

There is no need to include all headers. Enough to have only needed one.

Change-Id: I4813156404969df36f66c1102cd627fdc1e3e9dc
Signed-off-by: Michal Simek <michal.simek@amd.com>

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feat(xilinx): move IPI related macros to plat_ipi.h

The reason is to have all IPI related macros in the same file.

Change-Id: I88ddaa3a5dd1f10114371fc5405f8daf148ca3b8
Signed-off-by: Michal Simek <

feat(xilinx): move IPI related macros to plat_ipi.h

The reason is to have all IPI related macros in the same file.

Change-Id: I88ddaa3a5dd1f10114371fc5405f8daf148ca3b8
Signed-off-by: Michal Simek <michal.simek@amd.com>

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feat(versal-net): add the IPI CRC checksum macro support

Add support for CRC checksum for IPI data when the macro
IPI_CRC_CHECK is enabled.

Change-Id: I14dee4729f88c407bafdf1d6b46106459d8e22c4
Sign

feat(versal-net): add the IPI CRC checksum macro support

Add support for CRC checksum for IPI data when the macro
IPI_CRC_CHECK is enabled.

Change-Id: I14dee4729f88c407bafdf1d6b46106459d8e22c4
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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feat(xilinx): sync copyright format

Use the same format in all files 's/Copyright (C)/Copyright (c)/g'.

Change-Id: I0e200eb135e7369d0e6b3b694acd406ec10ca9e7
Signed-off-by: Michal Simek <michal.sime

feat(xilinx): sync copyright format

Use the same format in all files 's/Copyright (C)/Copyright (c)/g'.

Change-Id: I0e200eb135e7369d0e6b3b694acd406ec10ca9e7
Signed-off-by: Michal Simek <michal.simek@amd.com>

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Merge changes from topic "versal/xlat-v2" into integration

* changes:
feat(versal): switch to xlat_v2
fix(xilinx): remove asserts around arg0/arg1

fix(xilinx): remove asserts around arg0/arg1

The commit a6f340fe58b9 ("Introduce the new BL handover interface")
extended handoff to 4 registers instead of 2. Arguments arg0-3 are
not used by platfo

fix(xilinx): remove asserts around arg0/arg1

The commit a6f340fe58b9 ("Introduce the new BL handover interface")
extended handoff to 4 registers instead of 2. Arguments arg0-3 are
not used by platform code but in future they can be used for it.
But it doesn't make sense to checking their unused value.

Change-Id: I151e4b1574465409424453c054d937487086b79a
Signed-off-by: Michal Simek <michal.simek@amd.com>

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