| #
31ce893e |
| 23-Jan-2020 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
xilinx: versal: PLM to ATF handover
Parse the parameter structure the PLM populates, to populate the
bl32 and bl33 image structures.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xili
xilinx: versal: PLM to ATF handover
Parse the parameter structure the PLM populates, to populate the
bl32 and bl33 image structures.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I317072d1086f6cc6f90883c1b8b6d086ff57b443
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|
| #
f44d291f |
| 22-Jan-2020 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "add-versal-soc-support" into integration
* changes:
plat: xilinx: Move pm_client.h to common directory
plat: xilinx: versal: Make silicon default build target
xilinx:
Merge changes from topic "add-versal-soc-support" into integration
* changes:
plat: xilinx: Move pm_client.h to common directory
plat: xilinx: versal: Make silicon default build target
xilinx: versal: Wire silicon default setup
versal: Increase OCM memory size for DEBUG builds
plat: xilinx: versal: Dont set IOU switch clock
arm64: versal: Adjust cpu clock for versal virtual
xilinx: versal: Add support for PM_GET_OPERATING_CHARACTERISTIC EEMI call
plat: versal: Add Get_ChipID API
plat: xilinx: versal: Add load Pdi API support
xilinx: versal: Add feature check API
xilinx: versal: Implement set wakeup source for client
plat: xilinx: versal: Add GET_CALLBACK_DATA function
xilinx: versal: Add PSCI APIs for system shutdown & reset
xilinx: versal: Add PSCI APIs for suspend/resume
xilinx: versal: Remove no_pmc ops to ON power domain
xilinx: versal: Add set wakeup source API
xilinx: versal: Add client wakeup API
xilinx: versal: Add query data API
xilinx: versal: Add request wakeup API
xilinx: versal: Add PM_INIT_FINALIZE API for versal
xilinx: versal: Add support of PM_GET_TRUSTZONE_VERSION API
xilinx: versal: enable ipi mailbox service
xilinx: move ipi mailbox svc to xilinx common
plat: xilinx: versal: Implement PM IOCTL API
xilinx: versal: Implement power down/restart related EEMI API
xilinx: versal: Add SMC handler for EEMI API
xilinx: versal: Implement PLL related PM APIs
xilinx: versal: Implement clock related PM APIs
xilinx: versal: Implement pin control related PM APIs
xilinx: versal: Implement reset related PM APIs
xilinx: versal: Implement device related PM APIs
xilinx: versal: Add support for suspend related APIs
xilinx: versal: Add get_api_version support
xilinx: Add support to send PM API to PMC using IPI for versal
plat: xilinx: versal: Move versal_def.h to include directory
plat: xilinx: versal: Move versal_private.h to include directory
plat: xilinx: zynqmp: Use GIC framework for warm restart
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|
| #
d69bbd0e |
| 03-May-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
xilinx: versal: Wire silicon default setup
Add new option for serial and default clock setup.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.d
xilinx: versal: Wire silicon default setup
Add new option for serial and default clock setup.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I0ca7ad51637cdaa6bb891f22c53595d20da7236a
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| #
f8a650c1 |
| 25-Jun-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
plat: xilinx: versal: Dont set IOU switch clock
The IOU switch clock will be set by PLM during boot so there is no need to
set here and hence this patch removes it.
Signed-off-by: Siva Durga Prasad
plat: xilinx: versal: Dont set IOU switch clock
The IOU switch clock will be set by PLM during boot so there is no need to
set here and hence this patch removes it.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I1512708411eb07a07c1a8fbd66575efee975431a
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| #
c959c479 |
| 27-Apr-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: Adjust cpu clock for versal virtual
This patch modifies cpu clock for Xilinx Versal virtual
platform in order to keep same as used by QEMU.
Signed-off-by: Siva Durga Prasad Paladugu
arm64: versal: Adjust cpu clock for versal virtual
This patch modifies cpu clock for Xilinx Versal virtual
platform in order to keep same as used by QEMU.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I169d082462d7ce94a82c62966ab9eb122c5a3fee
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|
| #
5a8ffeab |
| 27-Feb-2019 |
Tejas Patel <tejas.patel@xilinx.com> |
xilinx: versal: Add PSCI APIs for suspend/resume
Add following APIs in plat_psci to support suspend resume:
- versal_pwr_domain_off
- versal_pwr_domain_suspend
- versal_pwr_domain_suspend_finish
- v
xilinx: versal: Add PSCI APIs for suspend/resume
Add following APIs in plat_psci to support suspend resume:
- versal_pwr_domain_off
- versal_pwr_domain_suspend
- versal_pwr_domain_suspend_finish
- versal_validate_power_state
- versal_get_sys_suspend_power_state
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Ife908a45f32e2037c9c19e13211a8e4b373b8342
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| #
fbb32695 |
| 09-Dec-2019 |
Tejas Patel <tejas.patel@xilinx.com> |
xilinx: versal: Add support for suspend related APIs
Add support for below suspend related APIs.
- self_suspend
- abort_suspend
- request_suspend
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
xilinx: versal: Add support for suspend related APIs
Add support for below suspend related APIs.
- self_suspend
- abort_suspend
- request_suspend
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: If568e0cd33b64754fe66f66fc0cdd0ec62c1b32e
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| #
c73a90e5 |
| 14-Dec-2018 |
Tejas Patel <tejas.patel@xilinx.com> |
xilinx: Add support to send PM API to PMC using IPI for versal
Port ZynqMP PM services for versal to send PM APIs to PMC
using IPI.
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by
xilinx: Add support to send PM API to PMC using IPI for versal
Port ZynqMP PM services for versal to send PM APIs to PMC
using IPI.
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Wendy Liang <wendy.liang@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I27a52faf27f1a2919213498276a6885a177cb6da
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| #
ab36d097 |
| 14-Dec-2018 |
Tejas Patel <tejas.patel@xilinx.com> |
plat: xilinx: versal: Move versal_def.h to include directory
Move versal_def.h to platform specific include directory.
Also, update source file to include header file from updated
path of versal_def
plat: xilinx: versal: Move versal_def.h to include directory
Move versal_def.h to platform specific include directory.
Also, update source file to include header file from updated
path of versal_def.h
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I313592a17552843b9cc7048f31bcaaefa40ffd91
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