1 /* 2 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef VERSAL_DEF_H 8 #define VERSAL_DEF_H 9 10 #include <plat/common/common_def.h> 11 12 /* List all consoles */ 13 #define VERSAL_CONSOLE_ID_pl011 1 14 #define VERSAL_CONSOLE_ID_pl011_0 1 15 #define VERSAL_CONSOLE_ID_pl011_1 2 16 #define VERSAL_CONSOLE_ID_dcc 3 17 18 #define VERSAL_CONSOLE_IS(con) (VERSAL_CONSOLE_ID_ ## con == VERSAL_CONSOLE) 19 20 /* List all supported platforms */ 21 #define VERSAL_PLATFORM_ID_versal_virt 1 22 23 #define VERSAL_PLATFORM_IS(con) (VERSAL_PLATFORM_ID_ ## con == VERSAL_PLATFORM) 24 25 /* Firmware Image Package */ 26 #define VERSAL_PRIMARY_CPU 0 27 28 /******************************************************************************* 29 * memory map related constants 30 ******************************************************************************/ 31 #define DEVICE0_BASE 0xFF000000 32 #define DEVICE0_SIZE 0x00E00000 33 #define DEVICE1_BASE 0xF9000000 34 #define DEVICE1_SIZE 0x00800000 35 36 /* CRL */ 37 #define VERSAL_CRL 0xFF5E0000 38 #define VERSAL_CRL_TIMESTAMP_REF_CTRL (VERSAL_CRL + 0x14C) 39 #define VERSAL_CRL_RST_TIMESTAMP_OFFSET (VERSAL_CRL + 0x348) 40 41 #define VERSAL_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT (1 << 25) 42 43 /* IOU SCNTRS */ 44 #define VERSAL_IOU_SCNTRS 0xFF140000 45 #define VERSAL_IOU_SCNTRS_COUNTER_CONTROL_REG (VERSAL_IOU_SCNTRS + 0x0) 46 #define VERSAL_IOU_SCNTRS_BASE_FREQ (VERSAL_IOU_SCNTRS + 0x20) 47 48 #define VERSAL_IOU_SCNTRS_CONTROL_EN 1 49 50 /******************************************************************************* 51 * IRQ constants 52 ******************************************************************************/ 53 #define VERSAL_IRQ_SEC_PHY_TIMER 29 54 55 /******************************************************************************* 56 * CCI-400 related constants 57 ******************************************************************************/ 58 #define PLAT_ARM_CCI_BASE 0xFD000000 59 #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4 60 #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 5 61 62 /******************************************************************************* 63 * UART related constants 64 ******************************************************************************/ 65 #define VERSAL_UART0_BASE 0xFF000000 66 #define VERSAL_UART1_BASE 0xFF010000 67 68 #if VERSAL_CONSOLE_IS(pl011) 69 # define VERSAL_UART_BASE VERSAL_UART0_BASE 70 #elif VERSAL_CONSOLE_IS(pl011_1) 71 # define VERSAL_UART_BASE VERSAL_UART1_BASE 72 #else 73 # error "invalid VERSAL_CONSOLE" 74 #endif 75 76 #define PLAT_VERSAL_CRASH_UART_BASE VERSAL_UART_BASE 77 #define PLAT_VERSAL_CRASH_UART_CLK_IN_HZ VERSAL_UART_CLOCK 78 #define VERSAL_CONSOLE_BAUDRATE VERSAL_UART_BAUDRATE 79 80 /******************************************************************************* 81 * Platform related constants 82 ******************************************************************************/ 83 #if VERSAL_PLATFORM_IS(versal_virt) 84 # define PLATFORM_NAME "Versal Virt" 85 # define VERSAL_UART_CLOCK 25000000 86 # define VERSAL_UART_BAUDRATE 115200 87 # define VERSAL_CPU_CLOCK 2720000 88 #endif 89 90 /* Access control register defines */ 91 #define ACTLR_EL3_L2ACTLR_BIT (1 << 6) 92 #define ACTLR_EL3_CPUACTLR_BIT (1 << 0) 93 94 /* For cpu reset APU space here too 0xFE5F1000 CRF_APB*/ 95 #define CRF_BASE 0xFD1A0000 96 #define CRF_SIZE 0x00600000 97 98 /* CRF registers and bitfields */ 99 #define CRF_RST_APU (CRF_BASE + 0X00000300) 100 101 #define CRF_RST_APU_ACPU_RESET (1 << 0) 102 #define CRF_RST_APU_ACPU_PWRON_RESET (1 << 10) 103 104 #define FPD_MAINCCI_BASE 0xFD000000 105 #define FPD_MAINCCI_SIZE 0x00100000 106 107 /* APU registers and bitfields */ 108 #define FPD_APU_BASE 0xFD5C0000 109 #define FPD_APU_CONFIG_0 (FPD_APU_BASE + 0x20) 110 #define FPD_APU_RVBAR_L_0 (FPD_APU_BASE + 0x40) 111 #define FPD_APU_RVBAR_H_0 (FPD_APU_BASE + 0x44) 112 #define FPD_APU_PWRCTL (FPD_APU_BASE + 0x90) 113 114 #define FPD_APU_CONFIG_0_VINITHI_SHIFT 8 115 #define APU_0_PWRCTL_CPUPWRDWNREQ_MASK 1 116 #define APU_1_PWRCTL_CPUPWRDWNREQ_MASK 2 117 118 /* IPI registers and bitfields */ 119 #define IPI0_REG_BASE 0xFF330000 120 #define IPI0_TRIG_BIT (1 << 2) 121 #define PMC_IPI_TRIG_BIT (1 << 1) 122 #define IPI1_REG_BASE 0xFF340000 123 #define IPI1_TRIG_BIT (1 << 3) 124 #define IPI2_REG_BASE 0xFF350000 125 #define IPI2_TRIG_BIT (1 << 4) 126 #define IPI3_REG_BASE 0xFF360000 127 #define IPI3_TRIG_BIT (1 << 5) 128 #define IPI4_REG_BASE 0xFF370000 129 #define IPI4_TRIG_BIT (1 << 5) 130 #define IPI5_REG_BASE 0xFF380000 131 #define IPI5_TRIG_BIT (1 << 6) 132 133 #endif /* VERSAL_DEF_H */ 134