1 /* 2 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef VERSAL_DEF_H 8 #define VERSAL_DEF_H 9 10 #include <plat/common/common_def.h> 11 12 /* List all consoles */ 13 #define VERSAL_CONSOLE_ID_pl011 1 14 #define VERSAL_CONSOLE_ID_pl011_0 1 15 #define VERSAL_CONSOLE_ID_pl011_1 2 16 #define VERSAL_CONSOLE_ID_dcc 3 17 18 #define VERSAL_CONSOLE_IS(con) (VERSAL_CONSOLE_ID_ ## con == VERSAL_CONSOLE) 19 20 /* List all supported platforms */ 21 #define VERSAL_PLATFORM_ID_versal_virt 1 22 23 #define VERSAL_PLATFORM_IS(con) (VERSAL_PLATFORM_ID_ ## con == VERSAL_PLATFORM) 24 25 /* Firmware Image Package */ 26 #define VERSAL_PRIMARY_CPU 0 27 28 /******************************************************************************* 29 * memory map related constants 30 ******************************************************************************/ 31 #define DEVICE0_BASE 0xFF000000 32 #define DEVICE0_SIZE 0x00E00000 33 #define DEVICE1_BASE 0xF9000000 34 #define DEVICE1_SIZE 0x00800000 35 36 /* CRL */ 37 #define VERSAL_CRL 0xFF5E0000 38 #define VERSAL_CRL_IOU_SWITCH_CTRL (VERSAL_CRL + 0x114) 39 #define VERSAL_CRL_TIMESTAMP_REF_CTRL (VERSAL_CRL + 0x14C) 40 #define VERSAL_CRL_RST_TIMESTAMP_OFFSET (VERSAL_CRL + 0x348) 41 42 #define VERSAL_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT (1 << 25) 43 #define VERSAL_IOU_SWITCH_CTRL_CLKACT_BIT (1 << 25) 44 #define VERSAL_IOU_SWITCH_CTRL_DIVISOR0_SHIFT 8 45 46 /* IOU SCNTRS */ 47 #define VERSAL_IOU_SCNTRS 0xFF140000 48 #define VERSAL_IOU_SCNTRS_COUNTER_CONTROL_REG (VERSAL_IOU_SCNTRS + 0x0) 49 #define VERSAL_IOU_SCNTRS_BASE_FREQ (VERSAL_IOU_SCNTRS + 0x20) 50 51 #define VERSAL_IOU_SCNTRS_CONTROL_EN 1 52 53 /******************************************************************************* 54 * IRQ constants 55 ******************************************************************************/ 56 #define VERSAL_IRQ_SEC_PHY_TIMER 29 57 58 /******************************************************************************* 59 * CCI-400 related constants 60 ******************************************************************************/ 61 #define PLAT_ARM_CCI_BASE 0xFD000000 62 #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4 63 #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 5 64 65 /******************************************************************************* 66 * UART related constants 67 ******************************************************************************/ 68 #define VERSAL_UART0_BASE 0xFF000000 69 #define VERSAL_UART1_BASE 0xFF010000 70 71 #if VERSAL_CONSOLE_IS(pl011) 72 # define VERSAL_UART_BASE VERSAL_UART0_BASE 73 #elif VERSAL_CONSOLE_IS(pl011_1) 74 # define VERSAL_UART_BASE VERSAL_UART1_BASE 75 #else 76 # error "invalid VERSAL_CONSOLE" 77 #endif 78 79 #define PLAT_VERSAL_CRASH_UART_BASE VERSAL_UART_BASE 80 #define PLAT_VERSAL_CRASH_UART_CLK_IN_HZ VERSAL_UART_CLOCK 81 #define VERSAL_CONSOLE_BAUDRATE VERSAL_UART_BAUDRATE 82 83 /******************************************************************************* 84 * Platform related constants 85 ******************************************************************************/ 86 #if VERSAL_PLATFORM_IS(versal_virt) 87 # define PLATFORM_NAME "Versal Virt" 88 # define VERSAL_UART_CLOCK 25000000 89 # define VERSAL_UART_BAUDRATE 115200 90 # define VERSAL_CPU_CLOCK 62500000 91 #endif 92 93 /* Access control register defines */ 94 #define ACTLR_EL3_L2ACTLR_BIT (1 << 6) 95 #define ACTLR_EL3_CPUACTLR_BIT (1 << 0) 96 97 /* For cpu reset APU space here too 0xFE5F1000 CRF_APB*/ 98 #define CRF_BASE 0xFD1A0000 99 #define CRF_SIZE 0x00600000 100 101 /* CRF registers and bitfields */ 102 #define CRF_RST_APU (CRF_BASE + 0X00000300) 103 104 #define CRF_RST_APU_ACPU_RESET (1 << 0) 105 #define CRF_RST_APU_ACPU_PWRON_RESET (1 << 10) 106 107 #define FPD_MAINCCI_BASE 0xFD000000 108 #define FPD_MAINCCI_SIZE 0x00100000 109 110 /* APU registers and bitfields */ 111 #define FPD_APU_BASE 0xFD5C0000 112 #define FPD_APU_CONFIG_0 (FPD_APU_BASE + 0x20) 113 #define FPD_APU_RVBAR_L_0 (FPD_APU_BASE + 0x40) 114 #define FPD_APU_RVBAR_H_0 (FPD_APU_BASE + 0x44) 115 #define FPD_APU_PWRCTL (FPD_APU_BASE + 0x90) 116 117 #define FPD_APU_CONFIG_0_VINITHI_SHIFT 8 118 #define APU_0_PWRCTL_CPUPWRDWNREQ_MASK 1 119 #define APU_1_PWRCTL_CPUPWRDWNREQ_MASK 2 120 121 /* IPI registers and bitfields */ 122 #define IPI0_REG_BASE 0xFF330000 123 #define IPI0_TRIG_BIT (1 << 2) 124 #define PMC_IPI_TRIG_BIT (1 << 1) 125 #define IPI1_REG_BASE 0xFF340000 126 #define IPI1_TRIG_BIT (1 << 3) 127 #define IPI2_REG_BASE 0xFF350000 128 #define IPI2_TRIG_BIT (1 << 4) 129 #define IPI3_REG_BASE 0xFF360000 130 #define IPI3_TRIG_BIT (1 << 5) 131 #define IPI4_REG_BASE 0xFF370000 132 #define IPI4_TRIG_BIT (1 << 5) 133 #define IPI5_REG_BASE 0xFF380000 134 #define IPI5_TRIG_BIT (1 << 6) 135 136 #endif /* VERSAL_DEF_H */ 137