Merge "fix(versal): modify IPI4 and IPI5 trigger bit definitions" into integration

fix(versal): modify IPI4 and IPI5 trigger bit definitions

The IPI4 and IPI5 trigger bit definitions are incorrect according
to the register database specification. This discrepancy can
cause IPI com

fix(versal): modify IPI4 and IPI5 trigger bit definitions

The IPI4 and IPI5 trigger bit definitions are incorrect according
to the register database specification. This discrepancy can
cause IPI communication failures between processing units in
Versal SoCs. So, modified the trigger bits to align the software
definitions with the hardware register specification as documented
in the register database.

Change-Id: I1e32961124daf8e5635906fb615e98a650130f27
Signed-off-by: Devanshi Chauhan <devanshi.chauhan@amd.com>

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Merge "chore(xilinx): reorder include files as per TF-A guidelines" into integration

chore(xilinx): reorder include files as per TF-A guidelines

This commit reorders the include files in accordance with the
guidelines provided by Trusted Firmware-A (TF-A).
The include files are rear

chore(xilinx): reorder include files as per TF-A guidelines

This commit reorders the include files in accordance with the
guidelines provided by Trusted Firmware-A (TF-A).
The include files are rearranged to ensure a consistent and
organized structure in the codebase, facilitating better
readability and maintainability.

https: //trustedfirmware-a.readthedocs.io/en/latest/process/coding-style.html#headers-and-inclusion
https://git.trustedfirmware.org/ci/tf-a-ci-scripts.git/tree/script/static-checks/

For example, to run header check:
/tf-a-ci-scripts/script/static-checks/check-include-order.py --tree ${PWD} > Includefileorder.txt

Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: Ia5802722e69859596b94f31ec40755adbf7d865b

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Merge changes from topic "xilinx-ipi" into integration

* changes:
feat(xilinx): fix IPI calculation for Versal/NET
feat(xilinx): setup local/remote id in header
feat(xilinx): clean macro names

Merge changes from topic "xilinx-ipi" into integration

* changes:
feat(xilinx): fix IPI calculation for Versal/NET
feat(xilinx): setup local/remote id in header
feat(xilinx): clean macro names
fix(zynqmp): do not export apu_ipi
fix(zynqmp): remove unused headers
feat(xilinx): move IPI related macros to plat_ipi.h

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feat(xilinx): fix IPI calculation for Versal/NET

Fix buffer calculation logic for Versal and Versal NET to use
LOCAL/REMOTE_ID.

Change-Id: Icf6985a19183cc8e51f3a536130695e00c32c736
Signed-off-by: M

feat(xilinx): fix IPI calculation for Versal/NET

Fix buffer calculation logic for Versal and Versal NET to use
LOCAL/REMOTE_ID.

Change-Id: Icf6985a19183cc8e51f3a536130695e00c32c736
Signed-off-by: Michal Simek <michal.simek@amd.com>

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feat(xilinx): setup local/remote id in header

Use new macros IPI_LOCAL_ID/IPI_REMOTE_ID to specify source and
destination channels.

Change-Id: I558eebb4d4a83ae0ca9316824f9dba7426adbe3f
Signed-off-b

feat(xilinx): setup local/remote id in header

Use new macros IPI_LOCAL_ID/IPI_REMOTE_ID to specify source and
destination channels.

Change-Id: I558eebb4d4a83ae0ca9316824f9dba7426adbe3f
Signed-off-by: Michal Simek <michal.simek@amd.com>

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feat(xilinx): clean macro names

This is preparation for cleaning up IPI local and remote side
communication. As of today macros are aligned to communication
channel but there is missing calculation

feat(xilinx): clean macro names

This is preparation for cleaning up IPI local and remote side
communication. As of today macros are aligned to communication
channel but there is missing calculation based on channel
selection.

Change-Id: Iac7daf832ff372ea2fece72a15afdfe988b4b7db
Signed-off-by: Michal Simek <michal.simek@amd.com>

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feat(xilinx): move IPI related macros to plat_ipi.h

The reason is to have all IPI related macros in the same file.

Change-Id: I88ddaa3a5dd1f10114371fc5405f8daf148ca3b8
Signed-off-by: Michal Simek <

feat(xilinx): move IPI related macros to plat_ipi.h

The reason is to have all IPI related macros in the same file.

Change-Id: I88ddaa3a5dd1f10114371fc5405f8daf148ca3b8
Signed-off-by: Michal Simek <michal.simek@amd.com>

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Merge changes from topic "versal-ipi" into integration

* changes:
fix(versal): fix incorrect regbase for PMC IPI
fix(versal): sync location based on IPI_ID macros
fix(xilinx): remove unused ma

Merge changes from topic "versal-ipi" into integration

* changes:
fix(versal): fix incorrect regbase for PMC IPI
fix(versal): sync location based on IPI_ID macros
fix(xilinx): remove unused mailbox macros

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fix(xilinx): remove unused mailbox macros

All these macro are unused that's why remove them.

Change-Id: I843cc7c1a592c47376a01c52f45b6d59da80772b
Signed-off-by: Michal Simek <michal.simek@amd.com>

Merge "fix(plat/xilinx/versal/include): correct IPI buffer offset" into integration

fix(plat/xilinx/versal/include): correct IPI buffer offset

Use proper offset for IPI data based on offset for IPI0
channel.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Abhyuday

fix(plat/xilinx/versal/include): correct IPI buffer offset

Use proper offset for IPI data based on offset for IPI0
channel.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: I3070517944dd353c3733aa595df0da030127751a

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Merge changes from topic "add-versal-soc-support" into integration

* changes:
plat: xilinx: Move pm_client.h to common directory
plat: xilinx: versal: Make silicon default build target
xilinx:

Merge changes from topic "add-versal-soc-support" into integration

* changes:
plat: xilinx: Move pm_client.h to common directory
plat: xilinx: versal: Make silicon default build target
xilinx: versal: Wire silicon default setup
versal: Increase OCM memory size for DEBUG builds
plat: xilinx: versal: Dont set IOU switch clock
arm64: versal: Adjust cpu clock for versal virtual
xilinx: versal: Add support for PM_GET_OPERATING_CHARACTERISTIC EEMI call
plat: versal: Add Get_ChipID API
plat: xilinx: versal: Add load Pdi API support
xilinx: versal: Add feature check API
xilinx: versal: Implement set wakeup source for client
plat: xilinx: versal: Add GET_CALLBACK_DATA function
xilinx: versal: Add PSCI APIs for system shutdown & reset
xilinx: versal: Add PSCI APIs for suspend/resume
xilinx: versal: Remove no_pmc ops to ON power domain
xilinx: versal: Add set wakeup source API
xilinx: versal: Add client wakeup API
xilinx: versal: Add query data API
xilinx: versal: Add request wakeup API
xilinx: versal: Add PM_INIT_FINALIZE API for versal
xilinx: versal: Add support of PM_GET_TRUSTZONE_VERSION API
xilinx: versal: enable ipi mailbox service
xilinx: move ipi mailbox svc to xilinx common
plat: xilinx: versal: Implement PM IOCTL API
xilinx: versal: Implement power down/restart related EEMI API
xilinx: versal: Add SMC handler for EEMI API
xilinx: versal: Implement PLL related PM APIs
xilinx: versal: Implement clock related PM APIs
xilinx: versal: Implement pin control related PM APIs
xilinx: versal: Implement reset related PM APIs
xilinx: versal: Implement device related PM APIs
xilinx: versal: Add support for suspend related APIs
xilinx: versal: Add get_api_version support
xilinx: Add support to send PM API to PMC using IPI for versal
plat: xilinx: versal: Move versal_def.h to include directory
plat: xilinx: versal: Move versal_private.h to include directory
plat: xilinx: zynqmp: Use GIC framework for warm restart

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xilinx: Add support to send PM API to PMC using IPI for versal

Port ZynqMP PM services for versal to send PM APIs to PMC
using IPI.

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by

xilinx: Add support to send PM API to PMC using IPI for versal

Port ZynqMP PM services for versal to send PM APIs to PMC
using IPI.

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Wendy Liang <wendy.liang@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I27a52faf27f1a2919213498276a6885a177cb6da

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