fix(xilinx): update dtb when dtb address and tf-a ddr flow is used

Memory reservation in dtb will be done only when TF-A runs from
ddr and dtb load address is provided.
Otherwise prepare_dtb will si

fix(xilinx): update dtb when dtb address and tf-a ddr flow is used

Memory reservation in dtb will be done only when TF-A runs from
ddr and dtb load address is provided.
Otherwise prepare_dtb will simply return.
Empty definition of prepare_dtb is removed.

Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Change-Id: Ie8a3ec51d60a7389831cfe6a112f722777930623

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fix(versal-net): add redundant call to avoid glitches

Add redundant macro call to increase security by making
code glitch immune as security operations might be
called with the IPI command.

Signed-

fix(versal-net): add redundant call to avoid glitches

Add redundant macro call to increase security by making
code glitch immune as security operations might be
called with the IPI command.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I84d84cca258b7cd981f62816c51032341e19095c

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fix(versal-net): change flag to increase security

Currently security flag is set to SECURE by default and
is changed to NON_SECURE if NS system is detected. In this
case NS system may access secure

fix(versal-net): change flag to increase security

Currently security flag is set to SECURE by default and
is changed to NON_SECURE if NS system is detected. In this
case NS system may access secure system if condition check
gets skipped due to glitches.

So, initialize security_flag to NON_SECURE_FLAG and switch
to SECURE_FLAG if the TrustZone bit is detected to be
in more secure state.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I7af54465bd8744ba97a58c02607631ee23619d47

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Merge "chore(xilinx): correct kernel doc warnings for missing functions" into integration

Merge "fix(xilinx): add headers to resolve compile time issue" into integration

fix(xilinx): add headers to resolve compile time issue

Add common/debug.h and libfdt.h files to the common file
for XILINX_OF_BOARD_DTB_ADDR configuration.

Signed-off-by: Akshay Belsare <akshay.bel

fix(xilinx): add headers to resolve compile time issue

Add common/debug.h and libfdt.h files to the common file
for XILINX_OF_BOARD_DTB_ADDR configuration.

Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Change-Id: I577cc018eda34e186e48594a62c54eb55f11bbd3

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fix(xilinx): remove clock_setrate and clock_getrate api

As per the current code base, PM_CLOCK_SETRATE and PM_CLOCK_GETRATE
APIs are not supported for the runtime operations in the firmware and
the

fix(xilinx): remove clock_setrate and clock_getrate api

As per the current code base, PM_CLOCK_SETRATE and PM_CLOCK_GETRATE
APIs are not supported for the runtime operations in the firmware and
the TF-A it is already returning an error when there is any request
to access these APIs. So, just removing the unused code to avoid the
confusion around these APIs.

Also, there is no issue with the backward compatibility as these APIs
were never used since implemented. Hence no need to bump up the
version of the feature check API as well.

Signed-off-by: Ronak Jain <ronak.jain@amd.com>
Change-Id: I444f973e62cd25aae2e7f697d808210b265106ad

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chore(xilinx): correct kernel doc warnings for missing functions

In commit b9d26cd3c4 ("chore(xilinx): replace fsbl with xbl"),
function and variable names were changed, but the corresponding
functi

chore(xilinx): correct kernel doc warnings for missing functions

In commit b9d26cd3c4 ("chore(xilinx): replace fsbl with xbl"),
function and variable names were changed, but the corresponding
function name in the functional documentation comments is not updated.
Update the function and variable names as per the above commit.

Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: I7b777c21fe3673d29f809bf923eba38749f2c024

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feat(versal): ddr address reservation in dtb at runtime

When the TF-A is placed in DDR memory range, the DDR memory range
needs to be explicitly reserved in the default device tree.

A new build tim

feat(versal): ddr address reservation in dtb at runtime

When the TF-A is placed in DDR memory range, the DDR memory range
needs to be explicitly reserved in the default device tree.

A new build time parameter, XILINX_OF_BOARD_DTB_ADDR, is introduced.
The TF-A will reserve the DDR memory only when a valid DTB address
is provided to XILINX_OF_BOARD_DTB_ADDR during build.

Now the user has options, either manually reserve the desired DDR
address range for TF-A in device tree or let TF-A access and modify
the device tree, to reserve the DDR address range, in runtime using
the build parameter.

Change-Id: I4442a90e1cab5a3a115f4eeb8a7e09e247189ff0
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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Merge "chore(xilinx): reorder include files as per TF-A guidelines" into integration

Merge "fix(versal-net): correct device node indexes" into integration

fix(versal-net): correct device node indexes

Currently, the peripheral node indexes are incorrect
for Versal NET due to which incorrect node error is
generated and permission to set the device as wa

fix(versal-net): correct device node indexes

Currently, the peripheral node indexes are incorrect
for Versal NET due to which incorrect node error is
generated and permission to set the device as wakeup
source is failed. Correct Versal NET peripheral node
indexes to fix above issue.

Fixes: 662aafd6475e ("feat(xilinx): add device node indexes")
Change-Id: I4a2d76f375645e13512599a0272d9322ff6fafd3
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>

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chore(xilinx): update warning message

Update the Warning message to be more informative
about the warning being printed.

Change-Id: I923dc5dd760908844d5e1ac8542fd1b04c9f0af5
Signed-off-by: Akshay B

chore(xilinx): update warning message

Update the Warning message to be more informative
about the warning being printed.

Change-Id: I923dc5dd760908844d5e1ac8542fd1b04c9f0af5
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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feat(versal-net): add cluster check in handoff parameters

Versal NET platform supports multiple cpu clusters and the cluster
information for every partition contaning firmware component
is being pas

feat(versal-net): add cluster check in handoff parameters

Versal NET platform supports multiple cpu clusters and the cluster
information for every partition contaning firmware component
is being passed by PLM through handoff parameters to TF-A.

Function implementation for getting cluster value for the firmware
component partition in TF-A and check for the firmware component
being targeted to be executed on Cluster 0.

Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Change-Id: I8622699e12b0a9cda83ae46e2ad0a038ca377fda

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chore(xilinx): replace fsbl with xbl

The handoff functionality is common between platforms and all
platforms do not use fsbl terminology. Renaming handoff related code
to generic naming.

Signed-off

chore(xilinx): replace fsbl with xbl

The handoff functionality is common between platforms and all
platforms do not use fsbl terminology. Renaming handoff related code
to generic naming.

Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: Ic250af927f33c4fecbc2e6bab01b83a6dd2aab52
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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chore(xilinx): reorder include files as per TF-A guidelines

This commit reorders the include files in accordance with the
guidelines provided by Trusted Firmware-A (TF-A).
The include files are rear

chore(xilinx): reorder include files as per TF-A guidelines

This commit reorders the include files in accordance with the
guidelines provided by Trusted Firmware-A (TF-A).
The include files are rearranged to ensure a consistent and
organized structure in the codebase, facilitating better
readability and maintainability.

https: //trustedfirmware-a.readthedocs.io/en/latest/process/coding-style.html#headers-and-inclusion
https://git.trustedfirmware.org/ci/tf-a-ci-scripts.git/tree/script/static-checks/

For example, to run header check:
/tf-a-ci-scripts/script/static-checks/check-include-order.py --tree ${PWD} > Includefileorder.txt

Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: Ia5802722e69859596b94f31ec40755adbf7d865b

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chore(xilinx): follow kernel doc format for functional documentation

For TF-A, there is no format specified for functional documentation.
For AMD-Xilinx platforms, following kernel-doc format for th

chore(xilinx): follow kernel doc format for functional documentation

For TF-A, there is no format specified for functional documentation.
For AMD-Xilinx platforms, following kernel-doc format for the functional
documentation to make sure AMD-xilinx documentation is align with
actual code.

For example use kernel-doc from linux to call:
<linux>/scripts/kernel-doc -man -v 1 >/dev/null file...

Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: Idcc9def408b6c8da35b36f67ef82fc00890e998c

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Merge "chore(xilinx): replace ATF with TFA" into integration

chore(xilinx): replace ATF with TFA

Since the Arm Trusted Firmware(ATF) has been renamed to Trusted
Firmware-A (TF-A), replace all the instances of ATF from code comments,
macros, variables and func

chore(xilinx): replace ATF with TFA

Since the Arm Trusted Firmware(ATF) has been renamed to Trusted
Firmware-A (TF-A), replace all the instances of ATF from code comments,
macros, variables and functions to TF-A.

Change-Id: Iab448d96158612a3effb4e49943f8d6cb43aaad5
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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feat(versal): add support for SMCC ARCH SOC ID

Add support for SMCCC_ARCH_SOC_ID as per SMC Calling Convention for
Versal platform.
The SMCC ARCH SOC ID call is used by system software to obtain the

feat(versal): add support for SMCC ARCH SOC ID

Add support for SMCCC_ARCH_SOC_ID as per SMC Calling Convention for
Versal platform.
The SMCC ARCH SOC ID call is used by system software to obtain the SiP
defined SoC identification details.

Change-Id: I1466a9ad1bc8dde1cda516ddd3edbaa6a5941237
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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refactor(versal-net): move macros to common header

Move the macros to common header from platform specific folder, so that
the same macros can be re-used in other platforms.

Change-Id: I355b024f5e8

refactor(versal-net): move macros to common header

Move the macros to common header from platform specific folder, so that
the same macros can be re-used in other platforms.

Change-Id: I355b024f5e870c6fc104598bc571dbaa29503ae2
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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feat(xilinx): add support to get chipid

Add support for PM API SYS to get the chip ID from the target.
The API calls the IPI command to read the Chip idcode and revision.

Change-Id: Id4d7d812cbf77c

feat(xilinx): add support to get chipid

Add support for PM API SYS to get the chip ID from the target.
The API calls the IPI command to read the Chip idcode and revision.

Change-Id: Id4d7d812cbf77c5e2fc7785b8afb379214f8dd19
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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fix(tree): correct some typos

found using codespell (https://github.com/codespell-project/codespell).

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I1bfa797e3460adddeefa916bb68e22beddaf6

fix(tree): correct some typos

found using codespell (https://github.com/codespell-project/codespell).

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I1bfa797e3460adddeefa916bb68e22beddaf6373

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Merge "feat(xilinx): sync copyright format" into integration

feat(xilinx): sync copyright format

Use the same format in all files 's/Copyright (C)/Copyright (c)/g'.

Change-Id: I0e200eb135e7369d0e6b3b694acd406ec10ca9e7
Signed-off-by: Michal Simek <michal.sime

feat(xilinx): sync copyright format

Use the same format in all files 's/Copyright (C)/Copyright (c)/g'.

Change-Id: I0e200eb135e7369d0e6b3b694acd406ec10ca9e7
Signed-off-by: Michal Simek <michal.simek@amd.com>

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