Merge changes from topic "am62l-bl1" into integration

* changes:
feat(k3low): add BL1 platform definitions and integration for AM62L
feat(k3low): add AM62L DDR platform shim and EVM board config

Merge changes from topic "am62l-bl1" into integration

* changes:
feat(k3low): add BL1 platform definitions and integration for AM62L
feat(k3low): add AM62L DDR platform shim and EVM board config
feat(k3low): introduce Cadence LPDDR4 core driver for AM62L

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feat(k3low): add AM62L DDR platform shim and EVM board config

Rename the board directory from am62lx/ to am62lx-evm/ to reflect the
specific board variant, and introduce the EVM board configuration:

feat(k3low): add AM62L DDR platform shim and EVM board config

Rename the board directory from am62lx/ to am62lx-evm/ to reflect the
specific board variant, and introduce the EVM board configuration:

- board_config.c: pad-mux initialisation for MAIN/WKUP UART0 pins,
verified against the AM62L TRM (SPRUJB4A p.3976).
- board_def.h: board-level UART base and clock definitions.
- board_config.h: shared header declaring board_init().

Add the TI-authored AM62L DDRSS platform shim that wraps the Cadence
driver for this SoC:

- am62l_ddrss.c / am62l_ddrss.h: PSC power sequencing and DDR
initialisation flow calling the Cadence CTL/PHY/PI APIs.
- am62lx_ddr_config.c / am62lx_ddr_config.h: register data for the
AM62L DDRSS configuration.
- am62lx_skevm_lp4_50_800.h: machine-generated SK-EVM LPDDR4 register
values produced by the SysConfig DDR tool v0.10.30. This file should
be regenerated via that tool if board or timing parameters change.

New source files are intentionally unreferenced in platform.mk pending
the BL1 integration patch.

board.mk is introduced as a placeholder required by platform.mk's
include directive for BL31 builds; BL1_SOURCES will be added in the
next patch when BL1 support is wired in.

Change-Id: I8aff5eb1c2429646a701dc3b09821318bb6e73b9
Signed-off-by: Hari Nagalla <hnagalla@ti.com>

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