fix(rcar3): clear TCR_EL1 at the BL2 entry pointAccording to ARM DDI0601 2025-06 [1] TCR_EL1, Translation ControlRegister (EL1), all fields of TCR_EL1 do, on a Warm reset, (thisfield) resets to a
fix(rcar3): clear TCR_EL1 at the BL2 entry pointAccording to ARM DDI0601 2025-06 [1] TCR_EL1, Translation ControlRegister (EL1), all fields of TCR_EL1 do, on a Warm reset, (thisfield) resets to an architecturally UNKNOWN value.On some SoCs, after reset, this TCR_EL1 may not be 0, which in itselfis perfectly valid behavior. However, existing software may depend onTCR_EL1 being 0, and the UNKNOWN value may confuse such software.Reset TCR_EL1 to well defined value 0 at BL2 entrypoint to achievemaximum compatibility.[1] https://developer.arm.com/documentation/ddi0601/2025-06/AArch64-Registers/TCR-EL1--Translation-Control-Register--EL1-Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # update commit messageChange-Id: If3a1d40291b9b9768a8fc55e750bd742f3cc4ddc---Note: This is related to MR 25532 , but with reworked commit message and broken out from the large work-in-progress series.
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feat(rcar3): change MMU configurationsAlways enable MMU and control access protection.Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>Signed-off-by: Yoshifumi Hosoya <yosh
feat(rcar3): change MMU configurationsAlways enable MMU and control access protection.Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>Change-Id: I4ac997cda2985746b2bf97ab9e4e5ace600f43ca
Merge changes from topic "panic_cleanup" into integration* changes: refactor(bl31): use elx_panic for sysreg_handler64 refactor(aarch64): rename do_panic and el3_panic refactor(aarch64): remo
Merge changes from topic "panic_cleanup" into integration* changes: refactor(bl31): use elx_panic for sysreg_handler64 refactor(aarch64): rename do_panic and el3_panic refactor(aarch64): remove weak links to el3_panic refactor(aarch64): refactor usage of elx_panic refactor(aarch64): cleanup HANDLE_EA_EL3_FIRST_NS usage
refactor(aarch64): rename do_panic and el3_panicCurrent panic call invokes do_panic which calls el3_panic, but now panichandles only panic from EL3 anid clear separation to use lower_el_panic()wh
refactor(aarch64): rename do_panic and el3_panicCurrent panic call invokes do_panic which calls el3_panic, but now panichandles only panic from EL3 anid clear separation to use lower_el_panic()which handles panic from lower ELs.So now we can remove do_panic and just call el3_panic for all panics.Change-Id: I739c69271b9fb15c1176050877a9b0c0394dc739Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
build: always prefix section names with `.`Some of our specialized sections are not prefixed with the conventionalperiod. The compiler uses input section names to derive certain othersection name
build: always prefix section names with `.`Some of our specialized sections are not prefixed with the conventionalperiod. The compiler uses input section names to derive certain othersection names (e.g. `.rela.text`, `.relacpu_ops`), and these can bedifficult to select in linker scripts when there is a lack of adelimiter.This change introduces the period prefix to all specialized sectionnames.BREAKING-CHANGE: All input and output linker section names have been prefixed with the period character, e.g. `cpu_ops` -> `.cpu_ops`.Change-Id: I51c13c5266d5975fbd944ef4961328e72f82fc1cSigned-off-by: Chris Kay <chris.kay@arm.com>
feat(plat/rcar3): add process to back up X6 and X7 register's valueBecause the x6 and x7 registers will be overwritten by the callee function,added the processing the register's value push to/pop
feat(plat/rcar3): add process to back up X6 and X7 register's valueBecause the x6 and x7 registers will be overwritten by the callee function,added the processing the register's value push to/pop from stack memory.Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>Change-Id: I5351a008d3b208a30a8bc8651b8d9b4d1a02a8e8
plat: renesas: aarch64: Move to commonMove plat aarch64 code to common directory, so that the samecode can be re-used by both R-Car Gen3 and RZ/G2 platforms.Signed-off-by: Biju Das <biju.das.jz@
plat: renesas: aarch64: Move to commonMove plat aarch64 code to common directory, so that the samecode can be re-used by both R-Car Gen3 and RZ/G2 platforms.Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>Change-Id: I66265e5e68bfcf5c3534965fb3549a145c782b47