1 /* 2 * Copyright (c) 2021-2022, Stephan Gerhold <stephan@gerhold.net> 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <common/debug.h> 9 #include <drivers/delay_timer.h> 10 #include <lib/mmio.h> 11 12 #include "msm8916_pm.h" 13 14 #define CPU_PWR_CTL 0x4 15 #define APC_PWR_GATE_CTL 0x14 16 17 #define CPU_PWR_CTL_CLAMP BIT_32(0) 18 #define CPU_PWR_CTL_CORE_MEM_CLAMP BIT_32(1) 19 #define CPU_PWR_CTL_L1_RST_DIS BIT_32(2) 20 #define CPU_PWR_CTL_CORE_MEM_HS BIT_32(3) 21 #define CPU_PWR_CTL_CORE_RST BIT_32(4) 22 #define CPU_PWR_CTL_COREPOR_RST BIT_32(5) 23 #define CPU_PWR_CTL_GATE_CLK BIT_32(6) 24 #define CPU_PWR_CTL_CORE_PWRD_UP BIT_32(7) 25 26 #define APC_PWR_GATE_CTL_GHDS_EN BIT_32(0) 27 #define APC_PWR_GATE_CTL_GHDS_CNT(cnt) ((cnt) << 24) 28 29 /* Boot a secondary CPU core for the first time. */ 30 void msm8916_cpu_boot(uintptr_t acs) 31 { 32 uint32_t pwr_ctl; 33 34 VERBOSE("PSCI: Powering on CPU @ 0x%08lx\n", acs); 35 36 pwr_ctl = CPU_PWR_CTL_CLAMP | CPU_PWR_CTL_CORE_MEM_CLAMP | 37 CPU_PWR_CTL_CORE_RST | CPU_PWR_CTL_COREPOR_RST; 38 mmio_write_32(acs + CPU_PWR_CTL, pwr_ctl); 39 dsb(); 40 41 mmio_write_32(acs + APC_PWR_GATE_CTL, APC_PWR_GATE_CTL_GHDS_EN | 42 APC_PWR_GATE_CTL_GHDS_CNT(16)); 43 dsb(); 44 udelay(2); 45 46 pwr_ctl &= ~CPU_PWR_CTL_CORE_MEM_CLAMP; 47 mmio_write_32(acs + CPU_PWR_CTL, pwr_ctl); 48 dsb(); 49 50 pwr_ctl |= CPU_PWR_CTL_CORE_MEM_HS; 51 mmio_write_32(acs + CPU_PWR_CTL, pwr_ctl); 52 dsb(); 53 udelay(2); 54 55 pwr_ctl &= ~CPU_PWR_CTL_CLAMP; 56 mmio_write_32(acs + CPU_PWR_CTL, pwr_ctl); 57 dsb(); 58 udelay(2); 59 60 pwr_ctl &= ~(CPU_PWR_CTL_CORE_RST | CPU_PWR_CTL_COREPOR_RST); 61 mmio_write_32(acs + CPU_PWR_CTL, pwr_ctl); 62 dsb(); 63 64 pwr_ctl |= CPU_PWR_CTL_CORE_PWRD_UP; 65 mmio_write_32(acs + CPU_PWR_CTL, pwr_ctl); 66 dsb(); 67 } 68