1 /* 2 * Copyright (c) 2021, Stephan Gerhold <stephan@gerhold.net> 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef PLATFORM_DEF_H 7 #define PLATFORM_DEF_H 8 9 #include <plat/common/common_def.h> 10 11 /* 12 * There is at least 1 MiB available for BL31. However, at the moment the 13 * "msm8916_entry_point" variable in the data section is read through the 14 * 64 KiB region of the "boot remapper" after reset. For simplicity, limit 15 * the end of the data section (BL31_PROGBITS_LIMIT) to 64 KiB for now and 16 * the overall limit to 128 KiB. This could be increased if needed by placing 17 * the "msm8916_entry_point" variable explicitly in the first 64 KiB of BL31. 18 */ 19 #define BL31_LIMIT (BL31_BASE + SZ_128K) 20 #define BL31_PROGBITS_LIMIT (BL31_BASE + SZ_64K) 21 #define BL32_LIMIT (BL32_BASE + SZ_128K) 22 23 #define CACHE_WRITEBACK_GRANULE U(64) 24 #define PLATFORM_STACK_SIZE SZ_4K 25 26 /* CPU topology: single cluster with 4 cores */ 27 #define PLATFORM_CLUSTER_COUNT U(1) 28 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) 29 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ 30 PLATFORM_MAX_CPUS_PER_CLUSTER) 31 32 /* Power management */ 33 #define PLATFORM_SYSTEM_COUNT U(1) 34 #define PLAT_NUM_PWR_DOMAINS (PLATFORM_SYSTEM_COUNT + \ 35 PLATFORM_CLUSTER_COUNT + \ 36 PLATFORM_CORE_COUNT) 37 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 38 #define PLAT_MAX_RET_STATE U(2) 39 #define PLAT_MAX_OFF_STATE U(3) 40 41 /* Translation tables */ 42 #define MAX_MMAP_REGIONS 8 43 #define MAX_XLAT_TABLES 4 44 45 #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32) 46 #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32) 47 48 /* Timer frequency */ 49 #define PLAT_SYSCNT_FREQ 19200000 50 51 /* 52 * The Qualcomm QGIC2 implementation seems to have PIDR0-4 and PIDR4-7 53 * erroneously swapped for some reason. PIDR2 is actually at 0xFD8. 54 * Override the address in <drivers/arm/gicv2.h> to avoid a failing assert(). 55 */ 56 #define GICD_PIDR2_GICV2 U(0xFD8) 57 58 #endif /* PLATFORM_DEF_H */ 59