feat(qti): add TF-A BL2 common platform frameworkCurrently QTI pltforms only supports coreboot as the second stagebootloader. Lets enable support for TF-A BL2 as the common referencesecond stage
feat(qti): add TF-A BL2 common platform frameworkCurrently QTI pltforms only supports coreboot as the second stagebootloader. Lets enable support for TF-A BL2 as the common referencesecond stage bootloader which is able to support a variety of normalworld OS bootloaders (BL33) like edk2, U-Boot, coreboot-depthcharge etc.The common reference boot flow should look like following on QTIplatforms: PBL (ROM) -> XBL -> BL2 -> BL31 -> BL33 -> Normal world OS | --> BL32As of now XBL is performing DRAM initialization and loads two set ofimages for BL2 and FIP into DRAM from flash after performing secure bootchecks if enabled. Then BL2 does the FIP parsing from DRAM and loadspayloads at appropriate addresses as per the FIP configuration.Note here that BL2 image is loaded from TZ partition on UFS flash whichby default requires QTI secure boot checks.Change-Id: Ice73905bff39291fa417389cb84dabe455c3f0baSigned-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
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refactor(cpus): optimize CVE checkingThis patch replaces the use of EXTRA functionswith using erratum entries checkto verify CVE mitigation application for some ofthe SMCCC_ARCH_WORKAROUND_* cal
refactor(cpus): optimize CVE checkingThis patch replaces the use of EXTRA functionswith using erratum entries checkto verify CVE mitigation application for some ofthe SMCCC_ARCH_WORKAROUND_* calls.Previously, EXTRA functions were individually implemented foreach SMCCC_ARCH_WORKAROUND_*, an approach that becomes unmanageablewith the increasing number of workarounds.By looking up erratum entries for CVE check, the process is streamlined,reducing overhead associated with creating andmaintaining EXTRA functions for each new workaround.New Errata entries are created for SMC workarounds andthat is used to target cpus that are uniquely impactedby SMC workarounds.Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>Change-Id: I873534e367a35c99461d0a616ff7bf856a0000af
refactor(cpus): remove cpu specific errata funcsErrata printing is done directly via generic_errata_report.This commit removes the unused \_cpu\()_errata_reportfunctions for all cores, and remove
refactor(cpus): remove cpu specific errata funcsErrata printing is done directly via generic_errata_report.This commit removes the unused \_cpu\()_errata_reportfunctions for all cores, and removes errata_func from cpu_ops.Change-Id: I04fefbde5f0ff63b1f1cd17c864557a14070d68cSigned-off-by: Ryan Everett <ryan.everett@arm.com>
feat(plat/qti): fix to support cpu erratafix to support ARM CPU errata based on core used.Signed-off-by: Saurabh Gorecha <quic_sgorecha@quicinc.com>Change-Id: If1a438f98f743435a7a0b683a32ccf1416
feat(plat/qti): fix to support cpu erratafix to support ARM CPU errata based on core used.Signed-off-by: Saurabh Gorecha <quic_sgorecha@quicinc.com>Change-Id: If1a438f98f743435a7a0b683a32ccf14164db37e
feat(plat/qti/sc7280): support for qti sc7280 platnew qti platform sc7280 support additionSigned-off-by: Saurabh Gorecha <sgorecha@codeaurora.org>Change-Id: I3dd99d8744a6c313f7dfbbee7ae2cbd6f216
feat(plat/qti/sc7280): support for qti sc7280 platnew qti platform sc7280 support additionSigned-off-by: Saurabh Gorecha <sgorecha@codeaurora.org>Change-Id: I3dd99d8744a6c313f7dfbbee7ae2cbd6f21656c1
sc7180 platform supportAdding support for QTI CHIP SC7180 on ATFChange-Id: I0d82d3a378036003fbd0bc4784f61464bb76ea82Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org>Co-authored-by: Mauli
sc7180 platform supportAdding support for QTI CHIP SC7180 on ATFChange-Id: I0d82d3a378036003fbd0bc4784f61464bb76ea82Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org>Co-authored-by: Maulik Shah <mkshah@codeaurora.org>