feat(qemu): allow ARM_ARCH_MAJOR/MINOR override

An upcoming change to the RME support code will use atomic instructions
introduced in Armv8.1 in order to implement bitlocks. In order to do
this, the

feat(qemu): allow ARM_ARCH_MAJOR/MINOR override

An upcoming change to the RME support code will use atomic instructions
introduced in Armv8.1 in order to implement bitlocks. In order to do
this, the code needs to be built with appropriate -march compiler flag
(otherwise the assembler complains about invalid instructions). One way
to do this is specifying ARM_ARCH_MAJOR/MINOR version greater than 8.0,
which is what the main Makefile does when ENABLE_RME is set.

Allow the main Makefile to override the ARM_ARCH_MAJOR/MINOR variables
on the QEMU platform, so that it can also build the bitlock functions.

This only affects firmware built with ENABLE_RME, which is an
experimental feature both in TF-A and QEMU. The QEMU platform code
doesn't support booting an ENABLE_RME firmware on non-RME CPUs at the
moment.

As a result of this change, when ENABLE_RME is set,
make_helpers/arch_features.mk sets ENABLE_TRF_FOR_NS to 1, which needs
to be overridden by the QEMU Makefile.

Change-Id: I695fc98b21d07f6c84003d9e36a57cad2a3c806e
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>

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feat(qemu): enable FEAT_ECV when present

QEMU supports FEAT_ECV since commit 2808d3b38a52 ("target/arm: Implement
FEAT_ECV CNTPOFF_EL2 handling"), in the v9.0.0 release. Enable
auto-detecting the fe

feat(qemu): enable FEAT_ECV when present

QEMU supports FEAT_ECV since commit 2808d3b38a52 ("target/arm: Implement
FEAT_ECV CNTPOFF_EL2 handling"), in the v9.0.0 release. Enable
auto-detecting the feature on the QEMU platforms, in order to set
SCR.ECVEN. Without this, EL2 gets undefined instruction exceptions when
trying to access the new CNTPOFF register.

Change-Id: I555a5f9a9a84fd23e64ca85219ed1599204c6bb2
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>

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refactor(qemu): align image identifier string macros

Macros were renamed, align with new names.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: Iefcbf4aac9ce4b21f49a633749703f93d4e34250

refactor(qemu): console runtime switch on bl31 exit

Flush the FIFO before switching to runtime. This is so that there are
no lingering chars in the FIFO when we move to the runtime console.

TF-A pl

refactor(qemu): console runtime switch on bl31 exit

Flush the FIFO before switching to runtime. This is so that there are
no lingering chars in the FIFO when we move to the runtime console.

TF-A plans to refactor the console_Switch_state(CONSOLE_FLAG_RUNTIME)
and console_flush() calls and make them the last calls in bl31_main()
(before BL31 exits). Until then they are being left as the last calls
in bl31_plat_runtime_setup() for testing before refactoring.

This patch affects the QEMU platform only.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Change-Id: I6188d73dd3f3c97f41bb25de543f8c46a972adf0

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fix(qemu): disable FEAT_SB

qemu/qemu_sbsa platforms support wide selection of cpu cores. From
Cortex-A57 (v8.0) to Neoverse-N2 (v9.0) one. Only the last one (and
'max' which supports everything poss

fix(qemu): disable FEAT_SB

qemu/qemu_sbsa platforms support wide selection of cpu cores. From
Cortex-A57 (v8.0) to Neoverse-N2 (v9.0) one. Only the last one (and
'max' which supports everything possible) supports FEAT_SB.

Runtime check for ENABLE_FEAT_SB does not work in our case and we want
to have working platform.

Change-Id: Ic27d5af20ad76ae44c4211d28694e91ec62bddc1
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

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feat(qemu-sbsa): handle memory information

As a part of removing DeviceTree from EDK2, we move functions to TF-A:

- counting the number of memory nodes
- checking NUMA node id
- checking the memory

feat(qemu-sbsa): handle memory information

As a part of removing DeviceTree from EDK2, we move functions to TF-A:

- counting the number of memory nodes
- checking NUMA node id
- checking the memory address

Signed-off-by: Xiong Yining <xiongyining1480@phytium.com.cn>
Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn>
Change-Id: Ib7bce3a65c817a5b3bef6c9e0a459c7ce76c7e35

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feat(qemu): enable transfer list to BL31/32

Enable handoff to BL31 and BL32 using transfer list.
Encode TL_TAG_OPTEE_PAGABLE_PART as transfer entry.
Fallback to default handoff args when transfer li

feat(qemu): enable transfer list to BL31/32

Enable handoff to BL31 and BL32 using transfer list.
Encode TL_TAG_OPTEE_PAGABLE_PART as transfer entry.
Fallback to default handoff args when transfer list is disabled or
fails to archieve args from transfer entries.
Refactor handoff from BL2 to BL33.
Minor fixes of comment style.

Change-Id: I55d92ca7f5c4727bacc9725a7216c0ac70d16aec
Signed-off-by: Raymond Mao <raymond.mao@linaro.org>

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feat(qemu-sbsa): mpidr needs to be present

Coverity Scan reminded that we need to take care of MPIDR properly.
We need to make sure that we get MPIDR values from QEMU.

No MPIDR == panic() in case w

feat(qemu-sbsa): mpidr needs to be present

Coverity Scan reminded that we need to take care of MPIDR properly.
We need to make sure that we get MPIDR values from QEMU.

No MPIDR == panic() in case which should not happen.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: Idb5fe7d958f0bcecd3d66a643743f478538f4a8b

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docs(qemu-sbsa): describe what we get from QEMU

QEMU provides us with minimal information about hardware platform using
minimalistic DeviceTree. This is not a Linux DeviceTree. It is not even
a firm

docs(qemu-sbsa): describe what we get from QEMU

QEMU provides us with minimal information about hardware platform using
minimalistic DeviceTree. This is not a Linux DeviceTree. It is not even
a firmware DeviceTree.

Change-Id: I7b6cc5f53a4f78a9ed69bc7fc2fa1a69ea65428d
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

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feat(qemu-sbsa): handle CPU information

We want to remove use of DeviceTree from EDK2. So we move
functions to TF-A:

- counting cpu cores
- checking NUMA node id
- checking MPIDR

And then it gets

feat(qemu-sbsa): handle CPU information

We want to remove use of DeviceTree from EDK2. So we move
functions to TF-A:

- counting cpu cores
- checking NUMA node id
- checking MPIDR

And then it gets passed to EDK2 via SMC calls.

Change-Id: I1c7fc234ba90ba32433b6e4aa2cf127f26da00fd
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

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feat(qemu): support TRP for RME

When an external RMM is not provided during make invocation, include the
Test Realm Payload (TRP) to the FIP.

Change-Id: I15d396cf268a08d79da63075aadb4172238eb225
Si

feat(qemu): support TRP for RME

When an external RMM is not provided during make invocation, include the
Test Realm Payload (TRP) to the FIP.

Change-Id: I15d396cf268a08d79da63075aadb4172238eb225
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>

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feat(qemu): load and run RMM image

When RME is enabled, jump to the RMM image before BL33. When using
semihosting rather than FIP, the image called "rmm.bin" is loaded from
the runtime directory.

C

feat(qemu): load and run RMM image

When RME is enabled, jump to the RMM image before BL33. When using
semihosting rather than FIP, the image called "rmm.bin" is loaded from
the runtime directory.

Change-Id: I15863410b1e505aa502276b339b22a2ddcb0b745
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>

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feat(qemu): setup Granule Protection Table

When RME is enabled, call the GPT library to setup the granule
protection tables and partition the physical address space.

Change-Id: Ib466c4579ff55fcff93

feat(qemu): setup Granule Protection Table

When RME is enabled, call the GPT library to setup the granule
protection tables and partition the physical address space.

Change-Id: Ib466c4579ff55fcff9307550e6d26d432674779a
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>

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feat(qemu): setup memory map for RME

Reserve some space in DRAM for RMM, and some space in SRAM for the GPT
tables. Create the page table mappings.

Change-Id: I3822e7e505e86eb0fa15b1b5b6298e4122b17

feat(qemu): setup memory map for RME

Reserve some space in DRAM for RMM, and some space in SRAM for the GPT
tables. Create the page table mappings.

Change-Id: I3822e7e505e86eb0fa15b1b5b6298e4122b17181
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>

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feat(qemu): update mapping types for RME

With RME, mappings for EL3 use MT_ROOT rather than MT_SECURE. Update the
mapping types to select the right memory type: EL3_PAS is MT_ROOT when
RME is enable

feat(qemu): update mapping types for RME

With RME, mappings for EL3 use MT_ROOT rather than MT_SECURE. Update the
mapping types to select the right memory type: EL3_PAS is MT_ROOT when
RME is enabled, MT_SECURE otherwise.

Change-Id: I93e287009515b64e833a6f69545766be4c87e473
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>

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feat(qemu): use mock attestation functions for RME

Since QEMU doesn't yet emulate hardware attestation, provide hardcoded
key and token to demonstrate attestation for RME. They are copied from
the m

feat(qemu): use mock attestation functions for RME

Since QEMU doesn't yet emulate hardware attestation, provide hardcoded
key and token to demonstrate attestation for RME. They are copied from
the mock values for the FVP platform.

Change-Id: I9ce686955345854e9409af5c3aad2a648adea226
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>

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fix(qemu): increase max FIP size

The max FIP size for the QEMU virt platform is currently 4MB, which
isn't enough when including a RMM in the FIP. Since the secure flash
size is actually 64MB, we ca

fix(qemu): increase max FIP size

The max FIP size for the QEMU virt platform is currently 4MB, which
isn't enough when including a RMM in the FIP. Since the secure flash
size is actually 64MB, we can significantly increase the max FIP size.

Change-Id: Id2b5df355f8d4c90a41fec66f180e46eb7bab9f8
Fixes: a886bbeceb0d ("qemu: Update flash address map to keep FIP in secure FLASH0")
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>

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refactor(qemu): change way how we enable cpu features

We have to handle wide selection of cpu cores in one TF-A binary:
- v8.0: a53, a57, a72
- v8.2: a55, a76, n1
- v8.4: v1
- v9.0: a710, n2

And th

refactor(qemu): change way how we enable cpu features

We have to handle wide selection of cpu cores in one TF-A binary:
- v8.0: a53, a57, a72
- v8.2: a55, a76, n1
- v8.4: v1
- v9.0: a710, n2

And then we have QEMU's hybrid: 'max' which has everything QEMU can
emulate.

TF-A for QEMU platforms was built for v8.5 architecture. But turned out
that 'max' has v8.7 flag now (HCX) which we need to have. And this
enabled set of mandatory features which made TF-A not-bootable on
v8.0/8.2 cpus.

So I decided to follow Arm FVP way and do build for v8.0 with set of
feature flags enabled. This way we have bare minimum to make v8.0 cpus
boot. And then all features from newer cores are enabled with runtime
check which makes them boot.

Tested with BSA/SBSA ACS and Debian Linux 6.5 kernel.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: Ib87bdab992536c65ce0747ce1520682eafc18d39
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

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Merge "docs(qemu): mention a55 in list of v8.2 cores" into integration

Merge "build(qemu): use xlat tables v2 directly" into integration

build(qemu): use xlat tables v2 directly

Both qemu and qemu-sbsa use xlat tables v2 already (activated by including it
in common/common.mk) so there is no need to include compat headers.

Change-Id

build(qemu): use xlat tables v2 directly

Both qemu and qemu-sbsa use xlat tables v2 already (activated by including it
in common/common.mk) so there is no need to include compat headers.

Change-Id: I353a6f77f5916862e54b883a9adbba027ac81359
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

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docs(qemu): mention a55 in list of v8.2 cores

Change-Id: Ib3a1711be323023cf111373111f39038fa23fb6f
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

build(qemu-sbsa): it is GICv3 platform

GICV2_G0_FOR_EL3 variable is only for GICv2 platforms.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: Ibf9376caabbc05ceef4f870d8

build(qemu-sbsa): it is GICv3 platform

GICV2_G0_FOR_EL3 variable is only for GICv2 platforms.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: Ibf9376caabbc05ceef4f870d816e6c60a344f895

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feat(qemu): implement firmware handoff on qemu

Implement firmware handoff from BL2 to BL33 on qemu platform
compliant to Firmware handoff specification v0.9.

Change-Id: Id8d5206a71ef6ec97cf3c97995d

feat(qemu): implement firmware handoff on qemu

Implement firmware handoff from BL2 to BL33 on qemu platform
compliant to Firmware handoff specification v0.9.

Change-Id: Id8d5206a71ef6ec97cf3c97995de328ebf0600cc
Signed-off-by: Raymond Mao <raymond.mao@linaro.org>

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Merge "chore: remove MULTI_CONSOLE_API references" into integration