feat(plat/qemu): add sdei support for QEMU

Add sdei support for QEMU, this is to let jailhouse Hypervisor
use SDEI to do hypervisor management, after physical IRQ
has been disabled routing.

Note: T

feat(plat/qemu): add sdei support for QEMU

Add sdei support for QEMU, this is to let jailhouse Hypervisor
use SDEI to do hypervisor management, after physical IRQ
has been disabled routing.

Note: To enable SDEI in QEMU, it needs to set "SDEI_SUPPORT=1
EL3_EXCEPTION_HANDLING=1" when compiling.

Signed-off-by: Dongjiu Geng <gengdongjiu1@gmail.com>
Change-Id: Ia7f9c5a0db36da03e5c6e6fb1270281f19924d77

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feat(qemu-sbsa): handle GIC base

QEMU provides GIC information in DeviceTree (on platform version 0.1+).
Read it and provide to next firmware level via SMC.

Signed-off-by: Marcin Juszkiewicz <marci

feat(qemu-sbsa): handle GIC base

QEMU provides GIC information in DeviceTree (on platform version 0.1+).
Read it and provide to next firmware level via SMC.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I383919bd172acc8873292a0c5e4469651dc96fb9

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feat(qemu-sbsa): handle platform version

QEMU provides platform version information via DT. We want to use it
in firmware to handle differences between platform versions.

Signed-off-by: Marcin Jusz

feat(qemu-sbsa): handle platform version

QEMU provides platform version information via DT. We want to use it
in firmware to handle differences between platform versions.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I8def66dac9dd5d7ab0e459baa40e27a11b65f0ba

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fix(spmd): fix build error with spmd

Currently when we build with 'SPD=spmd SPMD_SPM_AT_SEL2=0'
options, this causes a build failure as
'plat_spmd_handle_group0_interrupt' is called irrespective of

fix(spmd): fix build error with spmd

Currently when we build with 'SPD=spmd SPMD_SPM_AT_SEL2=0'
options, this causes a build failure as
'plat_spmd_handle_group0_interrupt' is called irrespective of
'SPMD_SPM_AT_SEL2' usage in 'spmd_group0_interrupt_handler_nwd'

So make 'plat_spmd_handle_group0_interrupt' dummy implementation
available just when spmd is enabled and SPMC_AT_EL3 is disabled.

Change-Id: Iaccd38faab81671c98f9165f318145187dca9bc2
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge "fix(qemu-sbsa): enable FGT" into integration

feat(spmd): introduce platform handler for Group0 interrupt

This patch introduces a handler for FVP platform to triage Group0
secure interrupts. Currently, it is empty but serves as a
placeholder fo

feat(spmd): introduce platform handler for Group0 interrupt

This patch introduces a handler for FVP platform to triage Group0
secure interrupts. Currently, it is empty but serves as a
placeholder for future Group0 interrupt sources.

Moreover, this patch also provides a dummy implementation of the
above mentioned platform hook for QEMU, corstone100, n1sdp and
hikey960 ports.

Change-Id: I01d3451408f47ac313b0af74046cce89f89b85bb
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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fix(qemu-sbsa): enable FGT

QEMU 7.2+ has FEAT_FGT support added to 'max' cpu.

So let's enable it to make Debian 'bookworm' kernel boot on sbsa-ref/max setup.

Signed-off-by: Marcin Juszkiewicz <mar

fix(qemu-sbsa): enable FGT

QEMU 7.2+ has FEAT_FGT support added to 'max' cpu.

So let's enable it to make Debian 'bookworm' kernel boot on sbsa-ref/max setup.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I49fb3e742b69ce7be5666e0144525dde21a68238

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feat(qemu): increase max cpus per cluster to 16

Qemu-tcg with GICv3 emulation enabled will by default configure MPIDR
topology to report up to 16 cpus per cluster. This is NOT overriden by
qemu's -s

feat(qemu): increase max cpus per cluster to 16

Qemu-tcg with GICv3 emulation enabled will by default configure MPIDR
topology to report up to 16 cpus per cluster. This is NOT overriden by
qemu's -smp setting, e.g. -smp 8,clusters=2,cores=4,threads=1 will still
generate MPIDR reads as if all 8 CPUs were within one cluster.

Increase the hardcoded limit to reflect that so that we accept PSCI
calls that provide MPIDRs based on what was actually read from the
emulated CPU.

Change-Id: Ia321d555f885c96a9a94ae053b340e3a9e300e6d
Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>

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fix(qemu): enable dynamic feature detection of FEAT_SVE for NormalWorld

Currently, TF-A supports three states for feature flags:
0: FEAT_DISABLED
1: FEAT_STATE_ALWAYS ( for fixed/real platforms)
2:

fix(qemu): enable dynamic feature detection of FEAT_SVE for NormalWorld

Currently, TF-A supports three states for feature flags:
0: FEAT_DISABLED
1: FEAT_STATE_ALWAYS ( for fixed/real platforms)
2: FEAT_STATE_CHECK ( for configurable platforms)
to meet the feature detection requirements dynamically, mainly
targetting configurable/Fixed Virtual platforms.

With this mechanism in place, we are refactoring all the existing
feature flags to the FEAT_STATE_CHECK option(=2), including
FEAT_SVE explicitly for FVPs.

SVE Patch Reference:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/19888/25

This newly introduced change, breaks the existing behaviour especially
for virtual platforms, who have set the ENABLE_SVE_FOR_NS flag to 1.

Moving ahead, we advise the platforms to take the following steps while
enabling the features:

1. If the platform is configurable (virtual), and want to ensure feature
detection happens dynamically at runtime, set the build flags to
FEAT_STATE_CHECK(=2).

2. For real(fixed) platforms, depending on the features supported by the
hardware and platform wants to enable it, platforms could set build
flags to FEAT_STATE_ALWAYS(=1).

(Note: Only the non-secure world enablement related build flags have
been refactored to take the values within 0 to 2. As earlier Secure
world enablement flags will still remain boolean.)

Henceforth, in order to keep it aligned with this tri-state mechanism,
changing the qemu platform default to the now supported dynamic
option(=2), so the right decision can be made by the code at runtime.

Change-Id: Icc95b8b872378b7874d4345b631adfc314e4dada
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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Merge changes from topic "feat_state_part4" into integration

* changes:
refactor(cpufeat): enable FEAT_RNG for FEAT_STATE_CHECKED
refactor(cpufeat): align FEAT_SEL2 to new feature handling
ref

Merge changes from topic "feat_state_part4" into integration

* changes:
refactor(cpufeat): enable FEAT_RNG for FEAT_STATE_CHECKED
refactor(cpufeat): align FEAT_SEL2 to new feature handling
refactor(cpufeat): enable FEAT_NV2 for FEAT_STATE_CHECKED
refactor(cpufeat): enable FEAT_TWED for FEAT_STATE_CHECKED
refactor(cpufeat): enable FEAT_CSV2_2 for FEAT_STATE_CHECKED
refactor(cpufeat): enable FEAT_ECV for FEAT_STATE_CHECKED
refactor(cpufeat): enable FEAT_PAN for FEAT_STATE_CHECKED
refactor(cpufeat): align FEAT_SB to new feature handling
refactor(cpufeat): use alternative encoding for "SB" barrier
refactor(cpufeat): enable SYS_REG_TRACE for FEAT_STATE_CHECKED
fix(cpufeat): make stub enable functions "static inline"
fix(mpam): feat_detect: support major/minor

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fix(build): partially fix qemu aarch32 build

While aarch32 isn't currently supported on qemu, platform.mk contains
hard-coded references to aarch64 in BL1_SOURCES which should be ${ARCH}.

This impr

fix(build): partially fix qemu aarch32 build

While aarch32 isn't currently supported on qemu, platform.mk contains
hard-coded references to aarch64 in BL1_SOURCES which should be ${ARCH}.

This improves the situation, but since aarch32/qemu_max.S doesn't exist
and there are other missing files for aarch32, this is only a partial
fix.

Signed-off-by: Rebecca Cran <rebecca@quicinc.com>
Change-Id: I3fa01483e572abfd781ceaecff16ecf57cda8316

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refactor(cpufeat): enable FEAT_RNG for FEAT_STATE_CHECKED

At the moment we only support for FEAT_RNG to be either unconditionally
compiled in, or to be not supported at all.

Add support for runtime

refactor(cpufeat): enable FEAT_RNG for FEAT_STATE_CHECKED

At the moment we only support for FEAT_RNG to be either unconditionally
compiled in, or to be not supported at all.

Add support for runtime detection (FEAT_RNG=2), by splitting
is_armv8_5_rng_present() into an ID register reading function and a second
function to report the support status. That function considers both build
time settings and runtime information (if needed), and is used before we
access the RNDRRS system register.

Change the QEMU platform default to the now supported dynamic option (=2),
so the right decision can be made by the code at runtime.

Change-Id: I1a4a538d5ad395fead7324f297d0056bda4f84cb
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge "fix(pauth): make pauth_helpers linking generic" into integration

Merge changes from topics "qemu", "qemu_sbsa" into integration

* changes:
feat(qemu): add A76/N1 cpu support for virt
feat(qemu): add "neoverse-n1" cpu support
feat(qemu): make coherent memory

Merge changes from topics "qemu", "qemu_sbsa" into integration

* changes:
feat(qemu): add A76/N1 cpu support for virt
feat(qemu): add "neoverse-n1" cpu support
feat(qemu): make coherent memory section optional
refactor(qemu): make use of setup_page_tables()

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Merge "feat(qemu): combine TF-A artefacts into ROM file" into integration

feat(qemu): add A76/N1 cpu support for virt

Add support to "cortex-a76" and "neoverse-n1" cpu for "qemu" ('virt')
platform.

Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn>
Change-Id: I77a3e0bb

feat(qemu): add A76/N1 cpu support for virt

Add support to "cortex-a76" and "neoverse-n1" cpu for "qemu" ('virt')
platform.

Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn>
Change-Id: I77a3e0bb8397a2fb45a2caa7d93ba38e39297f93

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feat(qemu): add "neoverse-n1" cpu support

Add support to qemu "neoverse-n1" cpu for "qemu_sbsa" ('sbsa-ref')
platform.

Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn>
Change-Id: I4620e879c7111

feat(qemu): add "neoverse-n1" cpu support

Add support to qemu "neoverse-n1" cpu for "qemu_sbsa" ('sbsa-ref')
platform.

Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn>
Change-Id: I4620e879c71115451ae91a1643812d89ec7c071f

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feat(qemu): make coherent memory section optional

Since CPUs such as cortex-a76 are hardware-assisted coherent, coherent
memory section is not required for them and should be an optional
section.

S

feat(qemu): make coherent memory section optional

Since CPUs such as cortex-a76 are hardware-assisted coherent, coherent
memory section is not required for them and should be an optional
section.

Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn>
Change-Id: I03c8e9148ca1780b8af92024359698f4452f7129

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refactor(qemu): make use of setup_page_tables()

Use the setup_page_tables() helper function to setup page tables.

Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn>
Change-Id: I0bca4e463ed68abf2e

refactor(qemu): make use of setup_page_tables()

Use the setup_page_tables() helper function to setup page tables.

Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn>
Change-Id: I0bca4e463ed68abf2ef1c79fc8e5cb2b635fcd1c

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fix(pauth): make pauth_helpers linking generic

Pauth is a generic Arm feature that can be enabled on any platform that
implements it. It only needs a platform specific key generation hook. As
such,

fix(pauth): make pauth_helpers linking generic

Pauth is a generic Arm feature that can be enabled on any platform that
implements it. It only needs a platform specific key generation hook. As
such, the generic Pauth enablement can be included in the generic build.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ibf32f79addab3515214594bb8d7168151b450f59

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build: always prefix section names with `.`

Some of our specialized sections are not prefixed with the conventional
period. The compiler uses input section names to derive certain other
section name

build: always prefix section names with `.`

Some of our specialized sections are not prefixed with the conventional
period. The compiler uses input section names to derive certain other
section names (e.g. `.rela.text`, `.relacpu_ops`), and these can be
difficult to select in linker scripts when there is a lack of a
delimiter.

This change introduces the period prefix to all specialized section
names.

BREAKING-CHANGE: All input and output linker section names have been
prefixed with the period character, e.g. `cpu_ops` -> `.cpu_ops`.

Change-Id: I51c13c5266d5975fbd944ef4961328e72f82fc1c
Signed-off-by: Chris Kay <chris.kay@arm.com>

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feat(qemu): combine TF-A artefacts into ROM file

At the moment the QEMU platform documentation asks users to combine
bl1.bin and fip.bin in a certain way to get an image that can be used on
the QEMU

feat(qemu): combine TF-A artefacts into ROM file

At the moment the QEMU platform documentation asks users to combine
bl1.bin and fip.bin in a certain way to get an image that can be used on
the QEMU command line.

Let the build system actually create those files already, if we provide
a non-secure payload (BL33), to simplify deployment and spare the user of
fragile operations.

Change-Id: Ia35f17b9d60aab41f0d53f1f73a1326a316c4950
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge "fix(qemu-sbsa): enable SVE and SME" into integration

Merge changes from topic "qemu_sel2" into integration

* changes:
docs(build): describes the SPMC_OPTEE build option
feat(qemu): support el3 spmc
feat(el3-spmc): make platform logical partition

Merge changes from topic "qemu_sel2" into integration

* changes:
docs(build): describes the SPMC_OPTEE build option
feat(qemu): support el3 spmc
feat(el3-spmc): make platform logical partition optional
feat(qemu): support s-el2 spmc
feat(qemu): update abi between spmd and spmc
fix(sptool): add dependency to SP image

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feat(qemu): support el3 spmc

Introduce additional defines needed when compiling the QEMU platform
with SPMC at EL3.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Change-Id: If6dbe41fa87

feat(qemu): support el3 spmc

Introduce additional defines needed when compiling the QEMU platform
with SPMC at EL3.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Change-Id: If6dbe41fa8761637e39579a1f6818dabc769c139

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