| a2047853 | 10-Sep-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
feat(plat/nxp/common): define default PSCI features if not defined
SoC code can define supported features, otherwise use default setting.
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: J
feat(plat/nxp/common): define default PSCI features if not defined
SoC code can define supported features, otherwise use default setting.
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I0f11498c1f7558ff0ec2d9b344f3f7a4f5489ced
show more ...
|
| 35efe7a4 | 10-Sep-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
feat(plat/nxp/common): define common macro for ARM registers
Define common register macro both for Cortex-A53 and Cortex-A72
because the code will be used by both Cortex platform.
Signed-off-by: Bi
feat(plat/nxp/common): define common macro for ARM registers
Define common register macro both for Cortex-A53 and Cortex-A72
because the code will be used by both Cortex platform.
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I485661bfe3ed4f214c403ff6af53dc6af1ddf089
show more ...
|
| 6cad59c4 | 10-Sep-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
feat(plat/nxp/common): add CCI and EPU address definition
Add CCI and EPU base address definiton for Chassis v3.2.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I13250555b6646c1e7ba2e9d
feat(plat/nxp/common): add CCI and EPU address definition
Add CCI and EPU base address definiton for Chassis v3.2.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I13250555b6646c1e7ba2e9d7c9efca8501f17b3a
show more ...
|
| 08695df9 | 20-Jul-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
refactor(plat/nxp): refine api to read SVR register
1. Refined struct soc_info_t definition.
2. Refined get_soc_info function.
3. Fixed some SVR persernality value.
4. Refined API to get cluster num
refactor(plat/nxp): refine api to read SVR register
1. Refined struct soc_info_t definition.
2. Refined get_soc_info function.
3. Fixed some SVR persernality value.
4. Refined API to get cluster numbers and cores per cluster.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I3c20611a523516cc63330dce4c925e6cda1e93c4
show more ...
|
| 1ca72295 | 24-Aug-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
refactor(plat/nxp): each errata use a seperate source file
Don't mix erratas together in one file.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Ib1671011b91a41b0653210e4706d62b7e946c642 |
| 9616db15 | 20-Jul-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
refactor(plat/nxp): use a unified errata api
Use a unfied API soc_errata() for each platforms,
add print a INFO message for each enabled errata,
so that it will be easy to check which errata is
enab
refactor(plat/nxp): use a unified errata api
Use a unfied API soc_errata() for each platforms,
add print a INFO message for each enabled errata,
so that it will be easy to check which errata is
enabled on current platform.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I5eab3f338db6b46c57cbad475819043fc60ca6d3
show more ...
|
| 64cadc16 | 20-Jul-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
refactor(plat/soc-lx2160): move errata to common directory
Will add more Erratas, some errata can be used for multiple
platforms, so move errata to be common code which can
be share between differen
refactor(plat/soc-lx2160): move errata to common directory
Will add more Erratas, some errata can be used for multiple
platforms, so move errata to be common code which can
be share between different platforms.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Ib149b3eac365bdb593331e9f38f0b89d92c9c0d1
show more ...
|
| e4d0fa0b | 25-Jun-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
refactor(plat/nxp/lx216x): refine variable definition
This patch will make BL2_BASE to be hex valaue but
not a shell command.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Iebb86a0b9bc8
refactor(plat/nxp/lx216x): refine variable definition
This patch will make BL2_BASE to be hex valaue but
not a shell command.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Iebb86a0b9bc8cab1676bd8e898cf4a1b6d16f472
show more ...
|
| 96e63ccf | 25-Jun-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
refactor(plat/nxp/lx216x): use common make variables
Some build variables have already defined in common
make helper file, use them directly.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-I
refactor(plat/nxp/lx216x): use common make variables
Some build variables have already defined in common
make helper file, use them directly.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I7fe6331160bfdf315924d4498d78b0a399eb2e89
show more ...
|
| 28b3221a | 27-Apr-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
feat(plat/nxp/lx2): add SUPPORTED_BOOT_MODE definition
Add macro of SUPPORTED_BOOT_MODE for board lx2160ardb, lx2160aqds,
lx2162aqds.
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Jiafe
feat(plat/nxp/lx2): add SUPPORTED_BOOT_MODE definition
Add macro of SUPPORTED_BOOT_MODE for board lx2160ardb, lx2160aqds,
lx2162aqds.
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I4451ca030eca79c9bc5fee928eec497a7f0e878c
show more ...
|
| cd1280ea | 27-Apr-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
feat(plat/nxp/common): add build macro for BOOT_MODE validation checking
1. Added the build macro "add_boot_mode_define".
2. Use the macro to validate current BOOT_MODE against the
pre-determined
feat(plat/nxp/common): add build macro for BOOT_MODE validation checking
1. Added the build macro "add_boot_mode_define".
2. Use the macro to validate current BOOT_MODE against the
pre-determined list of SUPPORTED_BOOT_MODE, so each platform
need to define the list: SUPPORTED_BOOT_MODE.
3. Reports error if BOOT_MODE is not in SUPPORTED_BOOT_MODE list,
or BOOT_MODE is not supported yet althoug it is in SUPPORTED_BOOT_MODE.
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I29be60ecdb19fbec1cd162e327cdfb30ba629b07
show more ...
|
| 9398841e | 05-Jan-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
refactor(plat/nxp/common): moved soc make-variables to new soc_common_def.mk
Move some soc make variables to new soc_common_def.mk,
then it can be reused by other platforms.
Signed-off-by: Jiafei P
refactor(plat/nxp/common): moved soc make-variables to new soc_common_def.mk
Move some soc make variables to new soc_common_def.mk,
then it can be reused by other platforms.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Ia30bd332c95b6475f1cfee2f03a8ed3892a9568d
show more ...
|
| 9663160d | 04-Jan-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
refactor(plat/nxp/lx216x): clean up platform configure file
Use common code in common file to configure platform.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I72fe22751f12b8a4996a7b9f
refactor(plat/nxp/lx216x): clean up platform configure file
Use common code in common file to configure platform.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I72fe22751f12b8a4996a7b9f75fae4c912ea86de
show more ...
|
| 5d5c3ff3 | 04-Jan-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
refactor(plat/nxp/common): moved plat make-variables to new plat_common_def.mk
Move some common make variables to new plat_common_def.mk,
then it can be reused by other platforms.
Signed-off-by: Ji
refactor(plat/nxp/common): moved plat make-variables to new plat_common_def.mk
Move some common make variables to new plat_common_def.mk,
then it can be reused by other platforms.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I37bd65b0f8124f63074fa03339f886c2cdb30bd3
show more ...
|
| f359a382 | 09-Dec-2020 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
nxp lx2160a-aqds: new plat based on soc lx2160a
New NXP platform lx2160a-qds:
- Based SoC lx2160a
- Board specific tuning for DDR init.
- Board specific Flash details.
Signed-off-by: Udit Agarwal <
nxp lx2160a-aqds: new plat based on soc lx2160a
New NXP platform lx2160a-qds:
- Based SoC lx2160a
- Board specific tuning for DDR init.
- Board specific Flash details.
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I500ddbe9e56c4af5f955da6ecbd4ddc5fbe89a12
show more ...
|
| eb2b193d | 09-Dec-2020 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
NXP lx2160a-rdb: new plat based on SoC lx2160a
New NXP platform lx2160a-rdb(Reference Design Board):
- Based SoC lx2160a
- Board specific tuning for DDR init.
- Board specific Flash details.
Signed
NXP lx2160a-rdb: new plat based on SoC lx2160a
New NXP platform lx2160a-rdb(Reference Design Board):
- Based SoC lx2160a
- Board specific tuning for DDR init.
- Board specific Flash details.
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I9c10dac9d5e67d44a2d94a7a27812220fdcc6ae3
show more ...
|
| 1f497308 | 09-Dec-2020 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
nxp lx2162aqds: new plat based on soc lx2160a
New NXP platform lx2162aqds:
- Based SoC lx2160a
- Board specific tuning for DDR init.
- Board specific Flash details.
Signed-off-by: Udit Agarwal <udi
nxp lx2162aqds: new plat based on soc lx2160a
New NXP platform lx2162aqds:
- Based SoC lx2160a
- Board specific tuning for DDR init.
- Board specific Flash details.
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I53bfff85398313082db77c77625cb2d40cd9b1b1
show more ...
|
| 9877084b | 09-Dec-2020 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
nxp: errata handling at soc level for lx2160a
SoC erratas are handled as part of this commit.
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I06f7594d19cc7fc89fe036a8a255300458cb36dd |
| 18498657 | 09-Dec-2020 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
nxp: make file for loading additional ddr image
- NXP SoC lx2160a needs additional ddr_fip.bin.
- There are three types of ddr image that can be created:
-- ddr_fip.mk for creating fip_ddr.bin im
nxp: make file for loading additional ddr image
- NXP SoC lx2160a needs additional ddr_fip.bin.
- There are three types of ddr image that can be created:
-- ddr_fip.mk for creating fip_ddr.bin image for normal boot.
-- ddr_fip_sb.mk for creating fip_ddr_sec.bin image for NXP CSF based
CoT/secure boot.
-- ddr_fip_tbbr.mk for creating fip_ddr_sec.bin image for MBEDTLS
CoT/secure boot.
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I24bff8d489f72da99f64cb79b2114faa9423ce8c
show more ...
|
| 87056d31 | 09-Dec-2020 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
nxp: adding support of soc lx2160a
* NXP SoC is 16 A-72 core SoC.
* SoC specific defines are defined in:
- soc.def
- soc.h
* Called for BL2 and BL31 setup, SoC specific setup are implemented in:
nxp: adding support of soc lx2160a
* NXP SoC is 16 A-72 core SoC.
* SoC specific defines are defined in:
- soc.def
- soc.h
* Called for BL2 and BL31 setup, SoC specific setup are implemented in:
- soc.c
* platform specific helper functions implemented at:
- aarch64/lx2160a_helpers.S
* platform specific functions used by 'plat/nxp/commpon/psci',
etc. are implemented at:
- aarch64/lx2160a.S
* platform specific implementation for handling PSCI_SYSTEM_RESET2:
- aarch64/lx2160a_warm_rst.S
Signed-off-by: rocket <rod.dorris@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: Ib40086f9d9079ed9b22967baff518c6df9f408b8
show more ...
|
| dc05e50b | 09-Dec-2020 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
nxp: deflt hdr files for soc & their platforms
- Default header files for:
-- plat/nxp/soc-lxxxx/include/soc.h uses:
--- soc_default_base_addr.h
--- soc_default_base_macros.h
-- plat/n
nxp: deflt hdr files for soc & their platforms
- Default header files for:
-- plat/nxp/soc-lxxxx/include/soc.h uses:
--- soc_default_base_addr.h
--- soc_default_base_macros.h
-- plat/nxp/soc-lxxxx/<$PLAT>/platform_def.h uses:
--- plat_default_def.h: Every macro define can be overidden.
-- include/common/tbbr/tbbr_img_def.h uses:
--- plat_tbbr_img_def.h: platform specific new FIP image macros.
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: Ic50003e27e87891be3cd18bdb4e14a1c7272d492
show more ...
|
| b53c2c5f | 09-Dec-2020 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
nxp: platform files for bl2 and bl31 setup
For NXP platforms:
- Setup files for BL2 and BL31
- Other supporting files.
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I36a1183a0652701
nxp: platform files for bl2 and bl31 setup
For NXP platforms:
- Setup files for BL2 and BL31
- Other supporting files.
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I36a1183a0652701bdede9e02d41eb976accbb017
show more ...
|
| 0f33f50e | 09-Dec-2020 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
nxp: warm reset support to retain ddr content
NXP: Added warm reset handler to handle SMC PSCI_SYSTEM_RESET2
raised from kernel (> 5.4).
As part of first cold boot, DDR training data is stored in N
nxp: warm reset support to retain ddr content
NXP: Added warm reset handler to handle SMC PSCI_SYSTEM_RESET2
raised from kernel (> 5.4).
As part of first cold boot, DDR training data is stored in NV storage.
As part of this SMC handling, following things are done:
- DDR is put in self-refresh mode to retain the content of DDR.
- Reset cause is saved.
- Reset is triggered.
On next boot to last warm-reset, DDR training is restored from
the NV storage.
Signed-off-by: Ashish Kumar <ashish.kumar@nxp.com>
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Signed-off-by: Priyanka Singh <priyanka.singh@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I8e4fb0824887af49e959c93825e2ab0ba887fc9d
show more ...
|
| 7c2d1779 | 09-Dec-2020 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
nxp: nv storage api on platforms
NV storage API(s) for NXP platforms, supported on:
- flexspi-nor
- SecMon - General Purpose Registers at Low-Power section,
retains their content if backe
nxp: nv storage api on platforms
NV storage API(s) for NXP platforms, supported on:
- flexspi-nor
- SecMon - General Purpose Registers at Low-Power section,
retains their content if backed by coined battery.
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: Id65dee4f28e7d6d2024407030039de33ebe0fa05
show more ...
|
| 99cd54f3 | 09-Dec-2020 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
nxp: supports two mode of trusted board boot
NXP SoC supports two TBB mode:
- MBED_TLS based
-- ROTK key hash is placed as part of the BL2 binary at section:
--- .rodata.nxp_rotpk_hash
-- S
nxp: supports two mode of trusted board boot
NXP SoC supports two TBB mode:
- MBED_TLS based
-- ROTK key hash is placed as part of the BL2 binary at section:
--- .rodata.nxp_rotpk_hash
-- Supporting non-volatile counter via SFP.
-- platform function used by TFA common authentication code.
- NXP CSF based
-- ROTK key deployment vary from MBEDTLS
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: Ib0f0bf024fd93de906c5d4f609383ae9e02b2fbc
show more ...
|