1# Copyright 2020-2021 NXP 2# 3# SPDX-License-Identifier: BSD-3-Clause 4# 5 6# Include build macros, for example: SET_NXP_MAKE_FLAG 7include plat/nxp/common/plat_make_helper/plat_build_macros.mk 8 9# Adding platform specific defines 10 11$(eval $(call add_define_val,BOARD,'"${BOARD}"')) 12 13ifeq (${POVDD_ENABLE},yes) 14$(eval $(call add_define,CONFIG_POVDD_ENABLE)) 15endif 16 17ifneq (${FLASH_TYPE},) 18$(eval $(call add_define,CONFIG_${FLASH_TYPE})) 19endif 20 21ifneq (${XSPI_FLASH_SZ},) 22$(eval $(call add_define_val,NXP_FLEXSPI_FLASH_SIZE,${XSPI_FLASH_SZ})) 23endif 24 25ifneq (${QSPI_FLASH_SZ},) 26$(eval $(call add_define_val,NXP_QSPI_FLASH_SIZE,${QSPI_FLASH_SZ})) 27endif 28 29ifneq (${NOR_FLASH_SZ},) 30$(eval $(call add_define_val,NXP_NOR_FLASH_SIZE,${NOR_FLASH_SZ})) 31endif 32 33 34ifneq (${FSPI_ERASE_4K},) 35$(eval $(call add_define_val,CONFIG_FSPI_ERASE_4K,${FSPI_ERASE_4K})) 36endif 37 38ifneq (${NUM_OF_DDRC},) 39$(eval $(call add_define_val,NUM_OF_DDRC,${NUM_OF_DDRC})) 40endif 41 42ifeq (${CONFIG_DDR_NODIMM},1) 43$(eval $(call add_define,CONFIG_DDR_NODIMM)) 44DDRC_NUM_DIMM := 1 45endif 46 47ifneq (${DDRC_NUM_DIMM},) 48$(eval $(call add_define_val,DDRC_NUM_DIMM,${DDRC_NUM_DIMM})) 49endif 50 51ifneq (${DDRC_NUM_CS},) 52$(eval $(call add_define_val,DDRC_NUM_CS,${DDRC_NUM_CS})) 53endif 54 55ifeq (${DDR_ADDR_DEC},yes) 56$(eval $(call add_define,CONFIG_DDR_ADDR_DEC)) 57endif 58 59ifeq (${DDR_ECC_EN},yes) 60$(eval $(call add_define,CONFIG_DDR_ECC_EN)) 61endif 62 63ifeq (${CONFIG_STATIC_DDR},1) 64$(eval $(call add_define,CONFIG_STATIC_DDR)) 65endif 66 67# Platform can control the base address for non-volatile storage. 68#$(eval $(call add_define_val,NV_STORAGE_BASE_ADDR,'${BL2_BIN_XSPI_NOR_END_ADDRESS} - 2 * ${NXP_XSPI_NOR_UNIT_SIZE}')) 69 70ifeq (${WARM_BOOT},yes) 71$(eval $(call add_define_val,PHY_TRAINING_REGS_ON_FLASH,'${BL2_BIN_XSPI_NOR_END_ADDRESS} - ${NXP_XSPI_NOR_UNIT_SIZE}')) 72endif 73