feat(s32g274ardb): add custom DDR FW UUID entry

Integrate support to add DDR FW to the final
FIP image via `fiptool`.

Add mechanism to allow platform specific image
UUID. Add DDR FW entries to toc_

feat(s32g274ardb): add custom DDR FW UUID entry

Integrate support to add DDR FW to the final
FIP image via `fiptool`.

Add mechanism to allow platform specific image
UUID. Add DDR FW entries to toc_entries and create
`plat_fiptool.mk` in order to enable the integration
of the DDR FW binary into the FIP image using
`fiptool` command.

Change-Id: I10c000025378206411ab70dbc5b2e745ffb01e5d
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>

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feat(s32g274a): move fip in a dedicated partition

Modify the deployment method for TF-A binaries on the SD card. To
simplify deployment, BL2 will be decorated with an IVT, making it a
bootable image

feat(s32g274a): move fip in a dedicated partition

Modify the deployment method for TF-A binaries on the SD card. To
simplify deployment, BL2 will be decorated with an IVT, making it a
bootable image, while fip.bin will be deployed as a raw MBR partition on
the SD card. This approach allows the FIP location to be auto-discovered
based on information found in the MBR. The partition ID where the image
is stored is set to partition zero but can be changed using the FIP_PART
makefile parameter. The GPT header cannot be used instead of MBR due to
the boot header on the S32G274A, which may overlap with the GPT reserved
area.

Change-Id: I26746023dba7788613a74ae69c86124b450e6bdb
Co-developed-by: Bogdan Roman <bogdan-gabriel.roman@nxp.com>
Signed-off-by: Bogdan Roman <bogdan-gabriel.roman@nxp.com>
Co-developed-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(s32g274ardb): initialize the IO buffer

Define and initialize the IO buffer that will be used by the uSDHC
driver to load images from the SD card.

Change-Id: I8d9712b1243a58fd6830f2682edbb9e661

feat(s32g274ardb): initialize the IO buffer

Define and initialize the IO buffer that will be used by the uSDHC
driver to load images from the SD card.

Change-Id: I8d9712b1243a58fd6830f2682edbb9e661d2f6b5
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(s32g274ardb): initialize the uSDHC driver

S32G2 and IMX share the same uSDHC controller. Therefore, it is
initialized during BL2 to facilitate the loading of subsequent boot
stages.

Change-Id:

feat(s32g274ardb): initialize the uSDHC driver

S32G2 and IMX share the same uSDHC controller. Therefore, it is
initialized during BL2 to facilitate the loading of subsequent boot
stages.

Change-Id: I223904c24a14a89ef676626b54a5937f39a17eda
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(s32g274a): enable MMU for BL2 stage

Enable the MMU and add two entries to map the BL2 code and data regions.
Additional mappings will be added dynamically, enhancing flexibility and
modularity

feat(s32g274a): enable MMU for BL2 stage

Enable the MMU and add two entries to map the BL2 code and data regions.
Additional mappings will be added dynamically, enhancing flexibility and
modularity during the porting process.

Change-Id: I107abf944dfdce9dcff47b08272a5001484de8a9
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(s32g274a): increase the number of MMU regions

Increase the maximum number of regions allocated by the translation
table library to accommodate the entries added in the next commits.

Change-Id:

feat(s32g274a): increase the number of MMU regions

Increase the maximum number of regions allocated by the translation
table library to accommodate the entries added in the next commits.

Change-Id: Ib0dd2d0dbc9b4a574367141a7c96d76dd08e2c7f
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(s32g274a): add ncore support

Ncore is a cache-coherent interconnect module. It enables the
integration of heterogenous coherent agents and non-coherent
agents in a chip. TF-A boots with the fir

feat(s32g274a): add ncore support

Ncore is a cache-coherent interconnect module. It enables the
integration of heterogenous coherent agents and non-coherent
agents in a chip. TF-A boots with the first core in isolation
to avoid crashes due to cache invalidation operations. Later,
it will disable the isolation and reconfigure the module every
time a new core is added or removed through PSCI.

Change-Id: Ida42db91b10be1e66c3b9b73674d1e37a61844dd
Signed-off-by: Dan Nica <dan.nica@nxp.com>
Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): enable UART clock

Before this change, the internal oscillator clocked the UART with a
frequency of 48MHz. With the necessary support added, the UART clock
rate is increased to 125MHz

feat(nxp-clk): enable UART clock

Before this change, the internal oscillator clocked the UART with a
frequency of 48MHz. With the necessary support added, the UART clock
rate is increased to 125MHz by changing the clock source from FIRC to
PERIPH PLL PHI3.

Change-Id: I3160dc6860ebf441c9bea8eaf9d8d12de48bd647
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(s32g274a): enable BL31 stage

Add BL31 prerequisites for the S32G274ARDB2 board to allow single-core
cold boot without MMU and PSCI services.

Change-Id: I8a10fd62f3cc9430083758043ea82e3803f6106

feat(s32g274a): enable BL31 stage

Add BL31 prerequisites for the S32G274ARDB2 board to allow single-core
cold boot without MMU and PSCI services.

Change-Id: I8a10fd62f3cc9430083758043ea82e3803f61060
Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@nxp.com>
Signed-off-by: Bogdan Roman <bogdan-gabriel.roman@nxp.com>
Signed-off-by: Andra-Teodora Ilie <andra.ilie@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(s32g274a): add S32G274ARDB2 board support

S32G274ARDB2 is a development board to showcase the capabilities of the
S32G2 SoC. It includes 4 ARM Cortex-A53 cores running at 1.0GHz, 4GBs
of DDR, a

feat(s32g274a): add S32G274ARDB2 board support

S32G274ARDB2 is a development board to showcase the capabilities of the
S32G2 SoC. It includes 4 ARM Cortex-A53 cores running at 1.0GHz, 4GBs
of DDR, accelerators for automotive networking and many other
peripherals.

The added support is minimal and only includes the BL2 stage, with no
MMU enabled. The FIP is preloaded by the BootROM in SRAM, and BL2 copies
BL31 and BL33 from FIP to their designated addresses.

Change-Id: Iedda23302768ab70d63787117c5f6f3c21eb9842
Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@nxp.com>
Signed-off-by: Dan Nica <dan.nica@nxp.com>
Signed-off-by: Andra-Teodora Ilie <andra.ilie@nxp.com>
Signed-off-by: Bogdan Roman <bogdan-gabriel.roman@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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