Tegra186: mce: fix return value for enum features ari

This patch fixes the incorrect return value that was being passed
back for the ENUM_FEATURES ARI call.

Change-Id: I3842c6ce27ea24698608830cf4c1

Tegra186: mce: fix return value for enum features ari

This patch fixes the incorrect return value that was being passed
back for the ENUM_FEATURES ARI call.

Change-Id: I3842c6ce27ea24698608830cf4c12cfa7ff64421
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: mce: clear reserved fields for ARI calls

This patch clears the unused or reserved ARI input registers
before issuing the actual ARI command.

Change-Id: I454b86566bfe088049a5c63527c1323d7b

Tegra186: mce: clear reserved fields for ARI calls

This patch clears the unused or reserved ARI input registers
before issuing the actual ARI command.

Change-Id: I454b86566bfe088049a5c63527c1323d7b25248a
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: memctrl_v2: get chip revision using platform identifiers

This patch switches to the functions which identify the underlying
platform in order to calculate the chip SKU.

Change-Id: I20cf56234

Tegra: memctrl_v2: get chip revision using platform identifiers

This patch switches to the functions which identify the underlying
platform in order to calculate the chip SKU.

Change-Id: I20cf5623465289ccfab28d6578efcf762bfeb456
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: mce: read MCE's firmware version on "real" platforms

This patch runs the MCE firmware's version check only if the underlying
platform has the capability to the run the firmware. MCE firmwa

Tegra186: mce: read MCE's firmware version on "real" platforms

This patch runs the MCE firmware's version check only if the underlying
platform has the capability to the run the firmware. MCE firmware is not
running on simulation platforms, identified by v0.3 or v0.6, read from the
Tegra Chip ID value.

Change-Id: I3b1788b1ee2a0d4464017bb879ac5792cb7022b8
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: use helper functions to get major/minor version

This patch uses helper functions to read the chips's major and minor
version values.

Change-Id: I5b2530a31af5ab3778a8aa63380def4e9f9ee6ec
S

Tegra186: use helper functions to get major/minor version

This patch uses helper functions to read the chips's major and minor
version values.

Change-Id: I5b2530a31af5ab3778a8aa63380def4e9f9ee6ec
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: memmap all UART controllers

This patch adds all the UART controllers to the memory map.

Change-Id: I035e55ca7bff0a96115102f2295981f9e3a5da6b
Signed-off-by: Varun Wadekar <vwadekar@nvidia.

Tegra186: memmap all UART controllers

This patch adds all the UART controllers to the memory map.

Change-Id: I035e55ca7bff0a96115102f2295981f9e3a5da6b
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: implement plat_get_syscnt_freq2()

Commit f3d3b316f82faa88e42f3d09c97cd9e52ac92599 replaced
plat_get_syscnt_freq by plat_get_syscnt_freq2 on all the
upstream platforms. This patch modifies

Tegra186: implement plat_get_syscnt_freq2()

Commit f3d3b316f82faa88e42f3d09c97cd9e52ac92599 replaced
plat_get_syscnt_freq by plat_get_syscnt_freq2 on all the
upstream platforms. This patch modifies the Tegra186 code
which is not present usptream, yet.

Change-Id: Ieda6168050a7769680a3a94513637fed03463a2d
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: smmu: disable TCU prefetch for all the 64 contexts

This patch disables TCU prefetch for all the contexts in order
to improve SMMU performance.

Change-Id: I82ca49a0e396d9f064f5c62a5f00c4b2101

Tegra: smmu: disable TCU prefetch for all the 64 contexts

This patch disables TCU prefetch for all the contexts in order
to improve SMMU performance.

Change-Id: I82ca49a0e396d9f064f5c62a5f00c4b2101d8459
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: handlers to get BL31 arguments from previous bootloader

This patch overrides the default handlers to get BL31 arguments from the
previous bootloader. The previous bootloader stores the poi

Tegra186: handlers to get BL31 arguments from previous bootloader

This patch overrides the default handlers to get BL31 arguments from the
previous bootloader. The previous bootloader stores the pointer to the
arguments in PMC secure scratch register #53.

BL31 is the first component running on the CPU, as there isn't a previous
bootloader. We set the RESET_TO_BL31 flag to enable the path which assumes
that there are no input parameters passed by the previous bootloader.

Change-Id: Idacc1df292a70c9c1cb4d5c3a774bd796175d5e8
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: delete 'Video Memory Carveout' handling

This patch removes duplicate code from the platform's SiP handler
routine for processing Video Memory Carveout region requests and
uses the common S

Tegra186: delete 'Video Memory Carveout' handling

This patch removes duplicate code from the platform's SiP handler
routine for processing Video Memory Carveout region requests and
uses the common SiP handler instead.

Change-Id: Ib307de017fd88d5ed3c816288327cae750a67806
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: memctrl_v2: TZRAM aperture configuration settings

This patch enables the configuration settings for the TZRAM
aperture by programming the base/size of the aperture and
restricting access to i

Tegra: memctrl_v2: TZRAM aperture configuration settings

This patch enables the configuration settings for the TZRAM
aperture by programming the base/size of the aperture and
restricting access to it. We allow only the CPU to read/write
by programming the access configuration registers to 0.

Change-Id: Ie16ad29f4c5ec7aafa972b0a0230b4790ad5619e
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: modify the return type for `plat_get_syscnt_freq()`

Commit c073fda1c692d7c74415d26fb483d6336330fcc0 upstream changed the
return type for `plat_get_syscnt_freq()` from uint64_t to unsigned

Tegra186: modify the return type for `plat_get_syscnt_freq()`

Commit c073fda1c692d7c74415d26fb483d6336330fcc0 upstream changed the
return type for `plat_get_syscnt_freq()` from uint64_t to unsigned
long long.

This patch modifies the return type for the Tegra186 platform.

Change-Id: Ic9e5c364b90972265576e271582a4347e5eaa6eb
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: Enable ECC and Parity Protection for A02p SKUs

This patch enables ECC and Parity Protection for Cortex-A57 CPUs during boot,
for Tegra186 A02p SKUs.

Change-Id: I8522a6cb61f5e4fa9e0471f558

Tegra186: Enable ECC and Parity Protection for A02p SKUs

This patch enables ECC and Parity Protection for Cortex-A57 CPUs during boot,
for Tegra186 A02p SKUs.

Change-Id: I8522a6cb61f5e4fa9e0471f558a0c3ee8078370e
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: mce: Uncore Perfmon ARI Programming

Uncore perfmon appears to the CPU as a set of uncore perfmon registers
which can be read and written using the ARI interface. The MCE code
sequence hand

Tegra186: mce: Uncore Perfmon ARI Programming

Uncore perfmon appears to the CPU as a set of uncore perfmon registers
which can be read and written using the ARI interface. The MCE code
sequence handles reads and writes to these registers by manipulating
the underlying T186 uncore hardware.

To access an uncore perfmon register, CPU software writes the ARI
request registers to specify

* whether the operation is a read or a write,
* which uncore perfmon register to access,
* the uncore perfmon unit, group, and counter number (if necessary),
* the data to write (if the operation is a write).

It then initiates an ARI request to run the uncore perfmon sequence in
the MCE and reads the resulting value of the uncore perfmon register
and any status information from the ARI response registers.

The NS world's MCE driver issues MCE_CMD_UNCORE_PERFMON_REQ command
for the EL3 layer to start the entire sequence. Once the request
completes, the NS world would receive the command status in the X0
register and the command data in the X1 register.

Change-Id: I20bf2eca2385f7c8baa81e9445617ae711ecceea
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: implement `get_target_pwr_state` handler

This patch implements the `get_target_pwr_state` handler for Tegra186
SoCs. The SoC port uses this handler to find out the cluster/system
state dur

Tegra186: implement `get_target_pwr_state` handler

This patch implements the `get_target_pwr_state` handler for Tegra186
SoCs. The SoC port uses this handler to find out the cluster/system
state during CPU_SUSPEND, CPU_OFF and SYSTEM_SUSPEND calls.

The MCE firmware controls the power state of the CPU/CLuster/System,
so we query it to get the state and act accordingly.

Change-Id: I86633d8d79aec7dcb405d2301ac69910f93110fe
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: mce: add the mce_update_cstate_info() helper function

This patch adds a helper function to the MCE driver to allow its
clients to issue UPDATE_CSTATE_INFO requests, without having to
setup

Tegra186: mce: add the mce_update_cstate_info() helper function

This patch adds a helper function to the MCE driver to allow its
clients to issue UPDATE_CSTATE_INFO requests, without having to
setup the CPU context struct.

We introduced a struct to encapsulate the request parameters, that
clients can pass on to the MCE driver. The MCE driver gets the
parameters from the struct and programs the hardware accordingly.

Change-Id: I02bce57506c4ccd90da82127805d6b564375cbf1
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Merge pull request #875 from vwadekar/tegra186-platform-support-v2

Tegra186 platform support v2

Merge pull request #870 from douglas-raillard-arm/dr/remove_asm_signed_test

Replace ASM signed tests with unsigned

Tegra186: reset CPU power state info while onlining

This patch resets the CPU power state info when we online any CPU. The
NS world software would re-init the CPU power state after the CPU gets
onli

Tegra186: reset CPU power state info while onlining

This patch resets the CPU power state info when we online any CPU. The
NS world software would re-init the CPU power state after the CPU gets
online anyways. This allows us to maintain proper CPU/cluster power
states in the MCE firmware at all times.

Change-Id: Ib24054f53df720a4f88d67b2cb5a2e036e475e14
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: fix recursion in included headers (tegra_def.h/platform_def.h)

This patch fixes the "Recursion in included headers" error flagged by
Coverity.

Fixes coverity errors "31858: Recursion in i

Tegra186: fix recursion in included headers (tegra_def.h/platform_def.h)

This patch fixes the "Recursion in included headers" error flagged by
Coverity.

Fixes coverity errors "31858: Recursion in included headers" and
"31857: Recursion in included headers"

Change-Id: Icf8838434b1808b396e743e47f59adc452546364
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: memctrl_v2: fix logic to calculate TZRAM_ADDR_HI bits

This patch fixes the logic to calculate the higher bits for TZRAM's base/end
addresses.

Fixes coverity error "31853: Wrong operator used

Tegra: memctrl_v2: fix logic to calculate TZRAM_ADDR_HI bits

This patch fixes the logic to calculate the higher bits for TZRAM's base/end
addresses.

Fixes coverity error "31853: Wrong operator used (CONSTANT_EXPRESSION_RESULT)"

Change-Id: Iff62ef18cba59cd41ad63a5c71664872728356a8
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Merge pull request #873 from dp-arm/dp/makefile-reorg

Move plat/common source file definitions to generic Makefiles

Tegra: memctrl_v2: program Video Memory carveout size in MBs

This patch fixes the programming logic for the Video memory carveout's
size. The Memory Controller expects the size in terms of MBs inste

Tegra: memctrl_v2: program Video Memory carveout size in MBs

This patch fixes the programming logic for the Video memory carveout's
size. The Memory Controller expects the size in terms of MBs instead
of bytes.

Change-Id: Ia8261b737448bae9a435fe21ab336126785d4279
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: memctrl_v2: no stream ID override for Security Engine

This patch removes stream ID override for the Security Engine
hardware block as its stream ID is programmed by the NS world
driver.

Orig

Tegra: memctrl_v2: no stream ID override for Security Engine

This patch removes stream ID override for the Security Engine
hardware block as its stream ID is programmed by the NS world
driver.

Original change by Mallikarjun Kasoju <mkasoju@nvidia.com>

Change-Id: Ia6523c1a1bb0a82bdeb878feb55670813899bdac
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: reset power state info during CPU_ON

This patch resets the power state info for CPUs when onlining,
as we set deepest power when offlining a core but that may not
be requested by non-secur

Tegra186: reset power state info during CPU_ON

This patch resets the power state info for CPUs when onlining,
as we set deepest power when offlining a core but that may not
be requested by non-secure sw which controls idle states. It
will re-init this info from non-secure software when the core
come online.

Original change by Prashant Gaikwad <pgaikwad@nvidia.com>

Change-Id: Id6c2fa2b821c7705aafbb561a62348c36fd3abd8
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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